microwatt.git
2020-08-06 Paul Mackerrascore: Implement the maddhd, maddhdu and maddld instructions
2020-08-06 Paul Mackerrascore: Implement the cmpeqb and cmprb instructions
2020-08-06 Paul Mackerrascore: Implement the bpermd instruction
2020-08-06 Paul Mackerrascore: Implement the setb instruction
2020-08-06 Paul Mackerrascore: Implement the mcrxrx instruction
2020-08-05 Paul Mackerrascore: Implement the TAR register and the bctar instruction
2020-08-05 Paul Mackerrasexecute1: Use r.<field> not v.<field> in countzero...
2020-08-05 Paul Mackerrasexecute1: Take an extra cycle for OE=1 multiply instruc...
2020-08-05 Paul Mackerrasmultiplier: Generalize interface to the multiplier
2020-07-22 Michael NeulingMerge pull request #233 from paulusmack/master
2020-07-20 Paul Mackerrasloadstore1: Better expression for store data formatting
2020-07-20 Paul Mackerrasloadstore1: Further tweaks to improve synthesis with...
2020-07-20 Paul Mackerrasdcache: Ease timing on wishbone data and byte selects
2020-07-20 Paul Mackerrasdecode1: Fix formatting
2020-07-20 Paul Mackerrasloadstore1: Separate address calculation for MMU to...
2020-07-20 Paul Mackerrasloadstore1: Generate busy signal earlier
2020-07-20 Paul Mackerrasdcache: Output separate done-without-error and error...
2020-07-20 Paul Mackerrasdcache: Ease timing on calculation of acks remaining
2020-07-20 Paul Mackerrasdcache: Improve timing of valid/done outputs
2020-07-14 Paul Mackerrascore: Don't generate logic for log data when LOG_LENGTH = 0
2020-07-14 Paul Mackerrascountzero: Faster algorithm for count leading/trailing...
2020-07-14 Paul MackerrasMMU: Improve timing of done signal back to loadstore1
2020-07-14 Paul Mackerrasdcache: Remove dependency of r1.wb.adr/dat/sel on...
2020-07-14 Paul Mackerrasdcache: Update TLB PLRU one cycle later
2020-07-14 Paul Mackerrasloadstore1: Eliminate two_dwords variable
2020-07-14 Paul Mackerrasexecute1: Ease timing on redirect_nia
2020-07-14 Paul Mackerrasdcache: Do PLRU update one cycle later
2020-07-14 Paul Mackerrasicache: Do PLRU update one cycle later
2020-07-14 Michael NeulingMerge pull request #232 from gromero/for-anton
2020-07-13 Gustavo RomeroEnhance hello_world
2020-07-09 Michael NeulingMerge pull request #228 from ozbenh/misc
2020-07-09 Michael NeulingMerge pull request #222 from iamjpn/master
2020-07-08 Jordan Niethetests: Add tests for the PVR
2020-07-08 Benjamin Herrenschmidtcorefile/nexys_video: Parameter fixes
2020-07-08 Benjamin Herrenschmidtfpga: nexys-video: Wire up core_alt_reset
2020-07-08 Benjamin Herrenschmidtnexys_video: Fix nexys-video build
2020-07-08 Benjamin Herrenschmidtspi: Send dummy clocks at boot
2020-07-08 Paul MackerrasMerge pull request #223 from mikey/ecp5
2020-07-07 Michael NeulingCreate github artifacts for ECP5 devices
2020-07-07 Michael NeulingAdd PLL for ECP5 device
2020-07-07 Anton BlanchardMerge pull request #220 from mikey/ghdl-makefile
2020-07-07 Anton BlanchardMerge pull request #209 from mikey/yosys
2020-07-07 Jordan Niethecore: Implement PVR register
2020-07-04 Michael NeulingUse $(GHDL) rather than ghdl in Makefile
2020-07-02 Michael NeulingAdd yosys/nextpnr ecp5 and verilog build to CI
2020-07-02 Michael NeulingAdd FPGA_TARGET=ECP5-EVN make option for synthesis...
2020-07-02 Michael NeulingAdd SYNTH_ECP5_FLAGS option for building
2020-07-02 Michael NeulingAdd ram file to synthesis build dependencies
2020-07-02 Michael NeulingAdd uart16550 files to yosys/nextpnr build
2020-07-02 Michael NeulingAdd uart16550 files from fusesoc
2020-07-02 Michael NeulingBuild to tmp file so nextpnr errors don't confuse make
2020-07-02 Michael NeulingFix building with yosys/nextpnr
2020-07-02 Michael NeulingAdd yosys builds files to gitignore
2020-07-02 Michael NeulingSend line feed if we get a carriage return in hello...
2020-06-30 Michael NeulingMerge pull request #216 from paulusmack/cfar
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-29 Paul Mackerrasexecute1: Do forwarding of the CR result to the next...
2020-06-29 Paul Mackerrasexecute1: Add latch to redirect path
2020-06-29 Paul Mackerraslogical: Only do output inversion for OP_AND, OP_OR...
2020-06-29 Paul Mackerrascore: Implement CFAR register
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550
2020-06-29 Michael NeulingMerge pull request #212 from ozbenh/liteeth
2020-06-29 Michael NeulingMerge pull request #214 from shingarov/fix-ld-target
2020-06-26 Boris ShingarovFix ld error in elf maketarget
2020-06-25 Benjamin Herrenschmidttests: Add updated micropython build with 16550 support
2020-06-25 Benjamin Herrenschmidtsim_console: Fix polling to check for POLLIN
2020-06-25 Benjamin Herrenschmidtuart: Make 16550 the default
2020-06-23 Benjamin Herrenschmidtsyscon: Add flag to indicate the timebase frequency
2020-06-23 Benjamin Herrenschmidtconsole: Add support for the 16550 UART
2020-06-23 Benjamin Herrenschmidtuart: Add a simulation model for the 16550 compatible...
2020-06-23 Benjamin Herrenschmidtuart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
2020-06-23 Benjamin Herrenschmidtconsole: Cleanup console API
2020-06-23 Benjamin Herrenschmidtuart: Import and hook up opencore 16550 compatible...
2020-06-23 Benjamin Herrenschmidtex1: Add SPR_TBU support
2020-06-23 Benjamin Herrenschmidtliteeth: Hook up LiteX LiteEth ethernet controller
2020-06-23 Michael NeulingMerge pull request #211 from shenki/spi-constraint
2020-06-23 Joel Stanleyspi: Fix dat_i_l constraints
2020-06-23 Michael NeulingMerge pull request #210 from ozbenh/xics
2020-06-22 Benjamin Herrenschmidtxics: Add support for reduced priority field size
2020-06-19 Benjamin Herrenschmidtxics: Add simple ICS
2020-06-19 Benjamin Herrenschmidtxics/icp: MFRR starts at 0xff not 0x00
2020-06-19 Benjamin Herrenschmidttests/xics: Ensure no compiler optimisations in delay()
2020-06-19 Benjamin Herrenschmidtxics: ICP should be big endian !
2020-06-19 Benjamin Herrenschmidttests: Fix Makefile.test to not allow host includes
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
2020-06-16 Paul Mackerrasfpga: Add a xilinx_specific fileset to microwatt.core
2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
2020-06-15 Paul Mackerrasexecute1: Reduce width of the result mux to help timing
2020-06-15 Paul Mackerrascore: Implement a simple branch predictor
2020-06-15 Paul Mackerrasdecode1: Improve timing for slow SPR decode path
2020-06-14 Paul Mackerrasdecode1: Add a stash buffer to the output
2020-06-14 Benjamin Herrenschmidtsoc: Slight cleanup of IRQ assignments
2020-06-14 Benjamin Herrenschmidtsoc: Rename uart_dat8 to uart0_dat8
2020-06-14 Benjamin Herrenschmidtsoc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
2020-06-13 Jonathan BalkindMinor refactor of icache to make less dependent on...
2020-06-13 Paul Mackerrasdcache: Reduce back-to-back store latency from 3 cycles...
2020-06-13 Benjamin Herrenschmidtsoc: Don't require dram wishbones signals to be wired...
2020-06-13 Benjamin Herrenschmidtsoc: Add defaults for some input signals
2020-06-13 Benjamin Herrenschmidtsoc: Remove unused RESET_LOW generic
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