litex.git
2015-02-28 Florent Kermarrecmisoclib: better organization (create cores categories...
2015-02-28 Florent Kermarrecgensoc: parameter check is now more restrictive, add...
2015-02-27 Florent Kermarrectest minicon with de0nano (OK) and fix missing self...
2015-02-27 Florent Kermarrecgensoc: move I/O for rom initialization to make.py
2015-02-27 Florent Kermarrectargets: add de0nano (100MHz, integrated bios and SDRAM)
2015-02-27 Florent Kermarrecmake.py fix indent
2015-02-27 Florent Kermarrecbios: we can now use -Ot with_rom True on targets to...
2015-02-27 Florent Kermarrectargets: fix MiniSoC
2015-02-27 Florent Kermarrecsdram: import dfi, lasmibus, wishbone2lasmi from Migen...
2015-02-27 Florent Kermarrecgensoc: make it more generic (a SoC does not necessaril...
2015-02-27 Florent Kermarrecreserve csr_map 0-->16 for gensoc internal csrs
2015-02-27 Florent Kermarrecuse cachesize reported in wishbone2lasmi
2015-02-27 Florent Kermarreccreate cpu dir and move lm32/mor1kx in it
2015-02-27 Florent Kermarrecmove memtest to sdram
2015-02-27 Florent Kermarrecreplace self._r_register by self._register in all CSR...
2015-02-27 Florent Kermarrecmake.py: avoid some actions in make all (do not flash...
2015-02-27 Florent Kermarrecgensoc: add check_cpu_memory_region and check_csr_regio...
2015-02-27 Florent Kermarrecliteeth: move doc
2015-02-27 Robert Jordensadd pipistrello target
2015-02-27 Robert Jordensgensoc: missing self.
2015-02-27 Sebastien BourdeauducqMerge branch 'master' of https://github.com/m-labs...
2015-02-26 Yann Sionneautarget/kc705: allow access to pll_sys signal before...
2015-02-26 Florent Kermarrecgensoc: cpus now directly add their verilog sources
2015-02-26 Florent Kermarrecgensoc: add mem_map and mem_decoder to avoid duplications
2015-02-26 Florent Kermarrecgensoc: get platform_id from platform
2015-02-26 Florent Kermarrectargets/simple: make it generic (no default_platform...
2015-02-26 Florent Kermarrecliteeth: fix example_designs generation
2015-02-26 Florent Kermarrecliteeth: fix import (from liteeth --> from misoclib...
2015-02-26 Florent Kermarrecmove files to liteeeth and create example_designs directory
2015-02-25 Sebastien Bourdeauducqremove litex submodule
2015-02-25 Sebastien Bourdeauducqmerge liteeth
2015-02-25 Sebastien Bourdeauducqmove files for misoc integration
2015-02-25 Florent Kermarrecphy/sim: generate sop/eop
2015-02-24 Florent Kermarrecadd sim phy
2015-02-22 Florent Kermarrectest: add make.py to replace static config.py file
2015-02-22 Florent Kermarrectty working
2015-02-22 Florent Kermarrecmac: add padding
2015-02-21 Florent Kermarrecdoc: remove IP
2015-02-21 Florent Kermarrecadd tty over udp (will need mac to insert padding)
2015-02-21 Florent Kermarrecremove MiSoC dependency
2015-02-18 Florent Kermarrecupdate LiteX
2015-02-18 Florent Kermarrectargets/kc705: fix csr address conflict on eth
2015-02-18 Florent Kermarrecadd LiteX external core and remove ethmac
2015-02-18 Florent Kermarrecremove verilog and move mxcrg.v to misoclib/mxcrg
2015-02-18 Florent Kermarrecmove lm32/mor1kx submodules to extcores
2015-02-18 Florent Kermarrecgensoc: call do_exit after SoC is built
2015-02-18 Florent Kermarrecupdate LiteScope
2015-02-18 Florent Kermarrecreadme/make.py: add powered by Migen
2015-02-17 Florent Kermarreclogo : add powered by Migen
2015-02-17 Florent Kermarreccreate BaseSoC as a basic example design and build...
2015-02-17 Florent Kermarrectest: we can now test regs with Etherbone
2015-02-16 Florent Kermarrecetherbone: fix addressing
2015-02-16 Florent Kermarrecmac: fix missing core csr generation
2015-02-14 Florent Kermarrecgensoc: add csr_data_width and csr_address_width as...
2015-02-14 Florent Kermarrecadd setup.py
2015-02-12 Florent Kermarrecupdate download instructions
2015-02-12 Florent Kermarrecsimplify litescope export with do_exit call
2015-02-12 Florent Kermarrecetherbone: reads OK on hardware
2015-02-12 Florent Kermarrecetherbone: writes OK on hardware
2015-02-12 Florent Kermarrecetherbone: add more debug signals
2015-02-12 Florent Kermarrecetherbone: probing OK on hardware
2015-02-12 Florent Kermarrecetherbone: simplify model usage
2015-02-12 Florent Kermarrecetherbone: create example design target
2015-02-12 Florent Kermarreccosmetic: define params before payload
2015-02-12 Florent Kermarrecetherbone_tb: add autocheck
2015-02-12 Florent Kermarreccode cleanup
2015-02-12 Florent Kermarrecmove generic modules to generic/__init__.py
2015-02-12 Florent Kermarrecetherbone: cleanup
2015-02-11 Florent Kermarrecetherbone_tb OK (will need cleanup)
2015-02-11 Florent Kermarrecetherbone: wishbone reads seems OK in simulation
2015-02-11 Florent Kermarrecetherbone: wishbone writes seems OK in simulation
2015-02-11 Florent Kermarrecetherbone: code wishbone master
2015-02-11 Florent Kermarrecetherbone: record wip
2015-02-11 Florent Kermarrecetherbone: add record depacketizer/packetizer (wip)
2015-02-11 Florent Kermarrecetherbone: add etherbone_tb, able to probe etherbone...
2015-02-11 Florent Kermarrecmodels: use .format everywhere
2015-02-11 Florent Kermarrecetherbone: cleanup model
2015-02-10 Florent Kermarrecetherbone: clean up ohwr dissector, Python model checke...
2015-02-10 Florent Kermarrecetherbone: add model skeleton
2015-02-10 Florent Kermarrecetherbone: add dissector from ohwr.org
2015-02-10 Florent Kermarrecetherbone: wip
2015-02-10 Florent Kermarrectest_udp: test loopback on port 6000 (dw=8) and port...
2015-02-10 Florent Kermarrectargets/udp: create udp loopback on port 8000 with...
2015-02-10 Florent Kermarrecphy: add hw_init_reset (useful when used without CPU)
2015-02-10 Florent Kermarreccreate Port class and remove connect method of mac...
2015-02-10 Florent Kermarrecmove more things to common files
2015-02-10 Florent Kermarrecgeneric: add crossbar and use it in mac/ip/udp
2015-02-10 Florent KermarrecREADME: use migen fork for now
2015-02-10 Florent Kermarrecudp/crossbar: add possibility to get port with dw ...
2015-02-10 Florent Kermarrecuse new Migen feature: payload_layout/param_layout
2015-02-10 Florent Kermarrecmake packetizer/depacketizer more generic (remove width...
2015-02-09 Florent Kermarrecdoc: init
2015-02-09 Florent Kermarrecetherbone: add skeleton
2015-02-09 Florent KermarrecREADME: update
2015-02-09 Florent Kermarrecicmp: replace fifo with packet buffer and reduce buffering
2015-02-09 Florent Kermarrecuse PacketBuffer for udp loopback
2015-02-09 Florent Kermarrecmac: fix gap inserter/checker
2015-02-09 Florent Kermarrecip: pipeline checksum to improve timings
2015-02-09 Florent Kermarrecimprove RX timings (make valid synchronous)
2015-02-09 Florent Kermarrecadd test_la.py
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