yosys.git
2019-10-07 Eddie HungUse "abc9_period" attribute for delay target
2019-10-07 Eddie HungGet rid of latch_* in write_xaiger
2019-10-07 Eddie HungUpdate comments in abc9_map.v
2019-10-07 Eddie HungRemove -D_ABC9
2019-10-07 Eddie HungRemove "write_xaiger -zinit"
2019-10-07 Eddie HungAdd comment on default flop init
2019-10-07 Eddie HungGet rid of output_port lookup
2019-10-06 Eddie HungDo not require changes to cells_sim.v; try and work...
2019-10-05 Eddie HungError if $currQ not found
2019-10-05 Eddie Hungabc -> abc9
2019-10-05 Eddie HungFix from merge
2019-10-05 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-05 Eddie HungAdd temporary `abc9 -nomfs` and use for `synth_xilinx...
2019-10-05 Eddie HungUse read_args for read_verilog
2019-10-05 Eddie HungRemove DSP48E1 from *_cells_xtra.v
2019-10-05 Eddie HungFix merge issues
2019-10-04 Eddie HungMerge remote-tracking branch 'origin/eddie/abc_to_abc9...
2019-10-04 Eddie HungFix xilinx_dsp for unsigned extensions
2019-10-04 Eddie HungFix for SigSpec() == SigSpec(State::Sx, 0) to be true...
2019-10-04 Eddie HungAdd Const::{begin,end,empty}()
2019-10-04 Eddie HungRename abc_* names/attributes to more precisely be...
2019-10-04 Eddie HungPanic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 Eddie HungOops
2019-10-04 Eddie HungOhmilord this wasn't added all this time!?!
2019-10-03 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 Eddie HungEnglish
2019-10-03 Clifford WolfChange smtbmc "Warmup failed" status to "PREUNSAT"
2019-10-03 Clifford WolfUpdate ABC to git rev 623b5e8
2019-10-03 Clifford WolfBump version
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 Clifford WolfAdd "check -allow-tbuf"
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-03 Eddie HungMerge pull request #1423 from YosysHQ/eddie/techmap_rep...
2019-10-03 Eddie Hunglog_dump() to support State enum
2019-10-02 Eddie HungAlso rename cells with _TECHMAP_REPLACE_. prefix, as...
2019-10-02 Eddie HungExtend test with renaming cells with prefix too
2019-10-02 Clifford WolfMerge pull request #1428 from YosysHQ/clifford/fixbtor
2019-10-02 Clifford WolfAdd "check -mapped"
2019-10-02 Clifford WolfFix btor back-end to use "state" instead of "input...
2019-10-01 Eddie HungMore fixes
2019-10-01 Eddie HungEscape Verilog identifiers for legality outside of...
2019-10-01 Miodrag MilanovićMerge pull request #1426 from YosysHQ/mmicko/fix_environ
2019-10-01 Miodrag MilanovicDefine environ, fixes #1424
2019-10-01 David Shahecp5: Fix shuffle_enable port
2019-10-01 David Shahecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 Eddie HungAdd test
2019-10-01 Eddie Hungtechmap wires named _TECHMAP_REPLACE_.<identifier>...
2019-10-01 Eddie HungNo need to punch ports at all
2019-09-30 Eddie HungResolve FIXME on calling proc just once
2019-09-30 Eddie HungCleanup $currQ from aigerparse
2019-09-30 Eddie HungRemove need for $currQ port connection
2019-09-30 Eddie HungAdd explanation to abc_map.v
2019-09-30 Eddie HungAdd quick test
2019-09-30 Eddie HungAdd -select option to aigmap
2019-09-30 Eddie HungCleanup
2019-09-30 Eddie HungAdd comment
2019-09-30 Eddie HungFix typo
2019-09-30 Eddie HungFix for svinterfaces
2019-09-30 Eddie Hungmodule->derive() to be lazy and not touch ast if alread...
2019-09-30 Eddie HungUse a cell_cache to instantiate once rather than opt_me...
2019-09-30 Eddie Hungscc call on active module module only, plus cleanup
2019-09-30 Eddie HungUse derived module
2019-09-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 Eddie HungUpdate doc for equiv_opt
2019-09-30 whitequarkMerge pull request #1406 from whitequark/connect_rpc
2019-09-30 Eddie HungMerge pull request #1397 from btut/fix/python_wrappers_...
2019-09-30 whitequarkrpc: new frontend.
2019-09-30 whitequarklibs: import json11.
2019-09-30 Miodrag MilanovićMerge pull request #1416 from YosysHQ/mmicko/frontend_b...
2019-09-30 Clifford WolfBump version
2019-09-30 Clifford WolfMerge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
2019-09-30 Clifford WolfMerge pull request #1417 from YosysHQ/clifford/fixasync...
2019-09-30 Clifford WolfFix $dlatch handling in async2sync
2019-09-30 Eddie HungAdd latch test modified from #1363
2019-09-30 Eddie HungAdd LDCE/LDPE sim library, remove from *cells_xtra...
2019-09-30 Marcin Kościelnickisynth_xilinx: Support latches, remove used-up FF init...
2019-09-30 Eddie HungMissing endmodule
2019-09-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 Eddie HungMerge pull request #1414 from hzeller/improve-replace...
2019-09-29 Eddie HungMerge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 Eddie HungFDCE_1 does not have IS_CLR_INVERTED
2019-09-29 Eddie HungFix "scc" call inside abc9 to consider all wires
2019-09-29 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 Miodrag MilanovicFix reading aig files on windows
2019-09-29 Miodrag MilanovicOpen aig frontend as binary file
2019-09-29 Miodrag MilanovićMerge pull request #1413 from YosysHQ/mmicko/backend_bi...
2019-09-29 Clifford WolfMerge pull request #1411 from aman-goel/YosysHQ-master
2019-09-29 Henner ZellerAvoid work in replace() if rules empty.
2019-09-29 Eddie HungBig rework; flop info now mostly in cells_sim.v
2019-09-28 Miodrag MilanovicAdd aiger and protobuf backends binary support
2019-09-28 Miodrag MilanovicSupport binary files for backends, fixes #1407
2019-09-28 Eddie HungFix box name
2019-09-28 Eddie HungUse abc_mergeability attr for "r" extension
2019-09-28 Eddie HungSplit ABC9 based on clocking only, add "abc_mergeabilit...
2019-09-28 Eddie HungFix infinite recursion
2019-09-28 Eddie HungAdd -select option to aigmap
2019-09-28 Eddie HungFix typo
2019-09-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
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