gem5.git
2012-07-27 Anthony GutierrezARM: fix value of MISCREG_CTR returned by readMiscReg()
2012-07-23 Andreas HanssonConfig: Use clock option in se/fs script and pass to...
2012-07-23 Andreas HanssonBridge: Use EventWrapper instead of Event subclass...
2012-07-23 Steve Reinhardttest: Update eio ref outputs due to recent changes
2012-07-23 Steve Reinhardttest: Restore eio ref files clobbered in rev 8800b05e1cb3.
2012-07-23 Nilay VaishRegression: Update stats due to changes to x86 cpuid...
2012-07-23 Nilay VaishX86 CPUID: Return false if unknown processor family
2012-07-21 Andreas HanssonRegression: Fix topologies path in failing pc-simple...
2012-07-19 Steve ReinhardtAdded tag stable_2012_06_28 for changeset f75ee4849c40
2012-07-19 Steve ReinhardtAdded tag stable_2012_02_02 for changeset 549b72de8f72
2012-07-12 Andreas HanssonMem: Make SimpleMemory single ported
2012-07-12 Andreas Hanssonscons: Add LIBRARY_PATH from the user environment to...
2012-07-12 Nilay VaishRegression: update ruby.stats file
2012-07-12 Nilay VaishRuby: remove config information from ruby.stats
2012-07-12 Nilay VaishRuby: remove some unused stuff from SLICC files
2012-07-11 Brad Beckmannx86: added page size in bytes tlb entry function
2012-07-11 Brad Beckmannruby: improved DRAM reset comment
2012-07-11 Brad Beckmannregress: ruby stat additions and config changes
2012-07-11 Marc Orrsyscall emulation: Add the futex system call.
2012-07-11 Brad Beckmannx86: logSize and lruSeq are now optional ckpt params
2012-07-11 Steve ReinhardtAdd hook to call map() on Process from python.
2012-07-11 Brad Beckmann# User Brad Beckmann <Brad.Beckmann@amd.com>
2012-07-11 Brad Beckmannruby: remove the cpu assumptions for the random tester
2012-07-11 Brad Beckmann# User Brad Beckmann <Brad.Beckmann@amd.com>
2012-07-11 Brad Beckmannimported patch jason/slicc-external-structure-fix
2012-07-11 Brad Beckmannruby: banked cache array resource model
2012-07-11 Joel Hestnessruby: tag and data cache access support
2012-07-11 Nuwan Jayasenaruby: adds reset function to Ruby memory controllers
2012-07-11 Nuwan Jayasenaruby: memory controllers now inherit from an abstract...
2012-07-11 Brad Beckmanncpu: added assertions to ensure the correct proxies...
2012-07-11 Brad Beckmannruby: changes how Topologies are created
2012-07-09 Andreas HanssonEventManager: Rename queue accessor and remove cast...
2012-07-09 Andreas HanssonMem: Make members relating to range and size constant
2012-07-09 Andreas HanssonPort: Hide the queue implementation in SimpleTimingPort
2012-07-09 Andreas HanssonStats: Updates due to bus changes
2012-07-09 Andreas HanssonPort: Align port names in C++ and Python
2012-07-09 Andreas HanssonBus: Make the default bus width 8 bytes instead of 64
2012-07-09 Andreas HanssonBus: Split the bus into separate request/response layers
2012-07-09 Andreas HanssonBus: Add a notion of layers to the buses
2012-07-09 Andreas HanssonBus: Replace tickNextIdle and inRetry with a state...
2012-07-09 Andreas HanssonPort: Make getAddrRanges const
2012-07-09 Andreas HanssonPort: Add getAddrRanges to master port (asking slave...
2012-07-09 Andreas HanssonPort: Add isSnooping to slave port (asking master port)
2012-07-09 Andreas HanssonPort: Move retry from port base class to Master/SlavePort
2012-07-09 Andreas HanssonFix: Address a few benign memory leaks
2012-07-02 Andreas Hanssongcc: Fix warnings for gcc 4.7 and clang 3.1
2012-06-29 Lena OlsonCache: Fix the LRU policy for classic memory hierarchy
2012-06-29 Uri WienerBus: enable non/coherent buses sub-classes
2012-06-29 Dam SunwooMem: fix master id assertion in cache_impl.hh
2012-06-29 Matt EvansStyle: Make style.py's invalid warning print which...
2012-06-29 Matt EvansMem: Fix a livelock resulting in LLSC/locked memory...
2012-06-29 Ali SaidiStats: Update stats for RAS and LRU fixes.
2012-06-29 Nathanael PremillieuO3: Track if the RAS has been pushed or not to pop...
2012-06-29 Ali SaidiARM: Fix identification of one RAS pop instruction.
2012-06-29 Ali SaidiCache: Only invalidate a line in the cache when an...
2012-06-29 Ali SaidiARM: Update version of linux we claim to be to 3.0.0.
2012-06-29 Ali SaidiARM: Fix issue with predicted next pc being wrong becau...
2012-06-27 Ali SaidiARM: Fix address range issue with VExpress EMM stable_2012_06_28
2012-06-20 Andreas Hanssonswig: Use SWIG from environment when determining version
2012-06-18 Andreas HanssonBuild: Point to the appropriate tcmalloc package
2012-06-11 Anthony Gutierrezconfigs: add run scripts for ics/gb versions of android...
2012-06-11 Anthony GutierrezARM: implement the ProcessInfo methods
2012-06-11 Ali Saidiscons: Make compiler version error more verbose and...
2012-06-11 Marc OrrRegression: Fix some bugs in simple-timing-mp-ruby.py.
2012-06-08 Andreas HanssonTiming CPU: Remove a redundant port pointer
2012-06-08 Andreas HanssonPower: Fix MaxMiscDestRegs which was set to zero
2012-06-07 Nilay VaishX86 TLB: Add a missing = sign
2012-06-07 Ali Saidimem: Delay deleting of incoming packets by one call.
2012-06-07 Jayneel GandhiX86 TLB: Fix for gcc 4.4.3
2012-06-07 Nilay VaishConfig: call to setWorkCountOptions() for all ISAs
2012-06-07 Nilay VaishConfig: Remove setMipsOptions
2012-06-07 Nilay VaishConfig: changes to a couple of error msgs
2012-06-05 Anthony Gutierrezcpu: Don't init simple and inorder CPUs if they are...
2012-06-05 Ali SaidiISA: Back-out NoopMachInst as a StaticInstPtr change.
2012-06-05 Ali Saidicpt: update some comments in the checkpoint migration...
2012-06-05 Ali Saidiall: Update stats for memory per master and total fix.
2012-06-05 William Wangstats: when applying an operation to two vectors sum...
2012-06-05 Dam SunwooMem: add per-master stats to physmem
2012-06-05 Geoffrey BlakeARM: Add PCIe support to VExpress_EMM model and remove...
2012-06-05 Chander SudanthiARM: removed extra white space
2012-06-05 Chander SudanthiARM: Fix MPIDR and MIDR register implementation.
2012-06-05 Chander SudanthiARM: PS2 encoding fix
2012-06-05 Ali Saidisim: Provide a framework for detecting out of data...
2012-06-05 Ali Saidistats: Add stats unittest for total calculations.
2012-06-05 Ali SaidiO3: Clean up the O3 structures and try to pack them...
2012-06-05 Ali Saidisim: Add support for tcmalloc if it's installed and...
2012-06-05 Ali Saidisim: Remove FastAlloc
2012-06-05 Ali SaidiARM: Fix over-eager assert in gic.
2012-06-05 Mitchell Hayengastats: Provide a mechanism to get a callback when stats...
2012-06-05 Ali SaidiARM: Fix compilation on ARM after Gabe's change.
2012-06-04 Gabe BlackISA: Turn the ExtMachInst NoopMachinst into the StaticI...
2012-06-04 Gabe BlackX86: Update stats for the CPUID change.
2012-06-04 Gabe BlackX86: Ensure that the CPUID instruction always writes...
2012-06-04 Gabe BlackX86: Ensure that the decoder's internal ExtMachInst...
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus
2012-05-09 Andreas HanssonStats: Fix stats to match output after changeset 8800b0...
2012-05-30 Andreas Hanssongcc: Small fixes to compile with gcc 4.7
2012-05-30 Andreas HanssonBus: Remove redundant packet parameter from isOccupied
2012-05-30 Andreas HanssonBus: Turn the PortId into a transport function parameter
2012-05-30 Andreas HanssonPacket: Unify the use of PortID in packet and port
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