litex.git
2013-03-15 Sebastien Bourdeauducqgenlib/cdc/MultiReg: implement rename_clock_domain...
2013-03-15 Sebastien Bourdeauducqgenlib/cdc/MultiReg: remove idomain
2013-03-15 Sebastien Bourdeauducqfhdl/specials: fix rename_clock_domain declarations
2013-03-15 Sebastien Bourdeauducqsim: remove PureSimulable (superseded by Module)
2013-03-15 Sebastien Bourdeauducqstructure: remove Fragment.call_sim
2013-03-15 Sebastien Bourdeauducqsim: compatibility with new ClockDomain API
2013-03-15 Sebastien BourdeauducqLocal clock domain example
2013-03-15 Sebastien BourdeauducqMake ClockDomains part of fragments
2013-03-14 Sebastien Bourdeauducqflow/actor/filter_endpoints: deterministic order
2013-03-13 Sebastien Bourdeauducqbank/csrgen/BankArray: create banks in sorted order
2013-03-13 Sebastien Bourdeauducqbank/description: modify reg/mem in-place
2013-03-12 Sebastien Bourdeauducqexamples/pytholite: use new APIs
2013-03-12 Sebastien Bourdeauducqsim/generic: support implicit get_fragment
2013-03-12 Sebastien Bourdeauducqvpi: make it work by default on Arch
2013-03-12 Sebastien Bourdeauducqexamples/basic: use new APIs
2013-03-12 Sebastien Bourdeauducqfhdl/verilog: implicit get_fragment
2013-03-12 Sebastien Bourdeauducqfhdl/specials/Memory: automatic name#
2013-03-12 Sebastien Bourdeauducqbank: automatic register naming
2013-03-12 Sebastien Bourdeauducqfhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 Sebastien Bourdeauducqfhdl/tracer: recognize LOAD_DEREF opcode
2013-03-11 Sebastien Bourdeauducqfhdl/tracer: remove leading underscores from names
2013-03-11 Sebastien BourdeauducqREADME: update
2013-03-11 Sebastien Bourdeauducqbus/asmibus: use implicit finalization
2013-03-10 Sebastien BourdeauducqFix Register name conflict between Pytholite and Bank
2013-03-10 Sebastien Bourdeauducqbank/eventmanager: use module and autoreg
2013-03-10 Sebastien Bourdeauducqbus/asmibus: use fhdl.module API
2013-03-10 Sebastien Bourdeauducqfhdl/module: replace autofragment
2013-03-10 Sebastien Bourdeauducqbank/description/AutoReg: check that get_memories and...
2013-03-09 Sebastien Bourdeauducqbank/csrgen: BankArray
2013-03-09 Sebastien Bourdeauducqbank/description: AutoReg
2013-03-09 Sebastien Bourdeauducqmigen/fhdl/autofragment: factorize
2013-03-09 Sebastien Bourdeauducqfhdl/autofragment: remove legacy functions
2013-03-09 Sebastien Bourdeauducqfhdl/tools/flat_iteration: generalize
2013-03-09 Sebastien Bourdeauducqfhdl/autofragment: fix submodules
2013-03-09 Sebastien Bourdeauducqfhdl/autofragment: empty build_fragment by default
2013-03-09 Sebastien BourdeauducqUse common definition for FinalizeError
2013-03-08 Sebastien Bourdeauducqcsr/SRAM: support for writes with memory widths larger...
2013-03-06 Sebastien Bourdeauducqfhdl/verilog: tristate outputs are always wire
2013-03-03 Sebastien Bourdeauducqbus/csr: support memories with larger word width than...
2013-03-03 Sebastien Bourdeauducqfhdl/autofragment: bugfixes + add auto_attr
2013-03-02 Sebastien Bourdeauducqfhdl/autofragment: FModule
2013-03-01 Sebastien Bourdeauducqcsr/SRAM: prefix page register with memory name
2013-02-27 Sebastien Bourdeauducqfhdl/verilog: insert reset before listing signals
2013-02-25 Sebastien Bourdeauducqbank/description: memprefix
2013-02-25 Sebastien Bourdeauducqfhdl/specials: allow setting memory name
2013-02-25 Sebastien Bourdeauducquio/ioo: fix specials
2013-02-24 Sebastien Bourdeauducqfhdl/specials/Instance: _printintbool -> verilog_printexpr
2013-02-23 Sebastien Bourdeauducqexamples/psync: cleanup
2013-02-23 Sebastien Bourdeauducqexamples/basic/psync: demonstrate the new features
2013-02-23 Sebastien Bourdeauducqgenlib: clock domain crossing elements
2013-02-23 Sebastien Bourdeauducqfhdl/verilog: support special lowering and overrides
2013-02-22 Sebastien Bourdeauducqexamples/fir: better filter
2013-02-22 Sebastien Bourdeauducqcorelogic -> genlib
2013-02-22 Sebastien Bourdeauducqfhdl: inline synthesis directive support
2013-02-22 Sebastien Bourdeauducqdoc: new 'specials' API
2013-02-22 Sebastien BourdeauducqNew 'specials' API
2013-02-19 Sebastien Bourdeauducqdoc: tristates
2013-02-19 Sebastien Bourdeauducqfhdl: TSTriple
2013-02-14 Sebastien Bourdeauducqfhdl: tristate support
2013-02-11 Sebastien Bourdeauducqfhdl/autofragment: from_attributes
2013-02-10 Sebastien Bourdeauducqdoc: fix signal desc layout
2013-02-10 Sebastien BourdeauducqMerge branch 'master' of github.com:milkymist/migen
2013-02-10 Sebastien Bourdeauducqdoc/dataflow: remove ActorNode
2013-02-10 Sebastien Bourdeauducqdoc/dataflow: remove ALA
2013-02-10 Sebastien Bourdeauducqdoc: multiple clock domains
2013-02-10 Sebastien Bourdeauducqdoc: do not inline examples as this never works with...
2013-02-10 Sebastien Bourdeauducqdoc: update to new Migen APIs
2013-02-09 Sebastien Bourdeauducqsim: default runner to Icarus Verilog
2013-02-09 Sebastien Bourdeauducqflow/perftools: finish removing ActorNode
2013-01-24 Sebastien Bourdeauducqfhdl/structure: store clock domain name
2013-01-23 Sebastien Bourdeauducqfhdl/verilog: fix spurious clock/reset signals on multi...
2013-01-05 Sebastien Bourdeauducqcorelogic: complex arithmetic support
2013-01-05 Sebastien Bourdeauducqfhdl: support nested statement lists
2012-12-19 Sebastien Bourdeauducqpytholite: fix bug with constant assignment to register
2012-12-19 Sebastien Bourdeauducqpytholite: prune unused registers
2012-12-18 Sebastien BourdeauducqDo not use super()
2012-12-16 Sebastien Bourdeauducqexamples/pytholite: fix imports
2012-12-14 Sebastien Bourdeauducqfhdl/tools: bitreverse
2012-12-14 Sebastien Bourdeauducqactorlib/sim/SimActor: do not drive busy low when gener...
2012-12-14 Sebastien BourdeauducqToken: support idle_wait
2012-12-14 Sebastien BourdeauducqMove Token to migen.flow.transactions
2012-12-12 Sebastien Bourdeauducqreplace some forgotten is_abstract()
2012-12-12 Sebastien BourdeauducqRemove ActorNode
2012-12-06 Sebastien BourdeauducqMerge branch 'master' of github.com:milkymist/migen
2012-12-06 Sebastien Bourdeauducqfhdl/structure: do not create Signal in Instance when...
2012-12-06 Sebastien Bourdeauducqelsewhere: do not create interface in default param
2012-12-06 Sebastien Bourdeauducqmigen/bank: do not create interface in default param
2012-12-06 Sebastien Bourdeauducqbus/csr: add SRAM
2012-12-06 Sebastien Bourdeauducqbank/csrgen: interface -> bus
2012-12-05 Sebastien Bourdeauducqbank/description: define reset value of read signal
2012-12-05 Sebastien Bourdeauducqactorlib/sim: drive busy high until generator is finished
2012-12-01 Sebastien Bourdeauducqbus/wishbone/sram: accept memories < 32 bits
2012-12-01 Sebastien Bourdeauducqbus/wishbone: add SRAM
2012-11-30 Sebastien Bourdeauducqpytholite: fix bit width of selection signal
2012-11-30 Sebastien Bourdeauducqpytholite: support signed registers
2012-11-29 Sebastien Bourdeauducqcorelogic/roundrobin: fix request width (again)
2012-11-29 Sebastien Bourdeauducqcorelogic/roundrobin: fix request width
2012-11-29 Sebastien BourdeauducqFix various errors from new bitwidth/signedness system...
2012-11-29 Sebastien Bourdeauducqfhdl/verilog: make signal behave as integers in arithme...
2012-11-29 Sebastien Bourdeauducqfhdl/structure: add unary minus
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