git.libre-soc.org Git - yosys.git/shortlog

2019-11-26	Eddie Hung	clkpart to use 'submod -hidden'	commit \| commitdiff \| tree
2019-11-26	Eddie Hung	Add -hidden option to submod	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	Fold loop	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	Do not sigmap keep bits inside write_xaiger	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	Fix debug	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	Merge remote-tracking branch 'origin/master' into xaig_dff	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	Special abc9_clock wire to contain only clock signal	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	abc9 to contain time call	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	abc9 to no longer to clock partitioning, operate on...	commit \| commitdiff \| tree
2019-11-25	Eddie Hung	clkpart to analyse async flops too	commit \| commitdiff \| tree
2019-11-25	Marcin Kościelnicki	clkbufmap: Add support for inverters in clock path.	commit \| commitdiff \| tree
2019-11-25	Marcin Kościelnicki	xilinx: Use INV instead of LUT1 when applicable	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/clkpart...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	More oopsies	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Conditioning abc9 on POs not accurate due to cells	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	For abc9, run clkpart before ff_map and after abc9	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/clkpart...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Print ".en=" only if there is an enable signal	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Escape IdStrings	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	More sane naming of submod	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Add -set_attr option, -unpart to take attr name	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/clkpart...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge branch 'xaig_dff' of github.com:YosysHQ/yosys...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Do not use log_signal() for empty SigSpec to prevent...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Call submod once, more meaningful submod names, ignore...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/clkpart...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge pull request #1520 from pietrmar/fix-1463	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/submod_po...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Remove redundant flatten	commit \| commitdiff \| tree
2019-11-23	Martin Pietryka	coolrunner2: remove spurious log_pop() call, fixes...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	submod to bitty rather bussy, for bussy wires used...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Stray dump	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Move clkpart into passes/hierarchy	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/submod_po...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Constant driven signals are also an input to submodules	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Add another test with constant driver	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/submod_po...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Oops	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/clkpart...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Only action if there is more than one clock domain	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Replace TODO	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Add testcase for signal used as part input part output	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	write_xaiger back to working with whole modules only	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Merge remote-tracking branch 'origin/eddie/submod_po...	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Cleanup spacing	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	sigmap(wire) should inherit port_output status of POs	commit \| commitdiff \| tree
2019-11-23	Eddie Hung	Add testcase	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Merge branch 'eddie/clkpart' into xaig_dff	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Brackets	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Entry in Makefile.inc	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Merge branch 'eddie/clkpart' into xaig_dff	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Add to CHANGELOG	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	New 'clkpart' to {,un}partition design according to...	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Revert "write_xaiger to not use module POs but only...	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Missing endmodule	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Merge pull request #1517 from YosysHQ/clifford/optmem	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Merge pull request #1515 from YosysHQ/clifford/svastuff	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Add "opt_mem" pass	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Add Verific support for SVA nexttime properties	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Improve handling of verific primitives in "verific...	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Add Verific SVA support for "always" properties	commit \| commitdiff \| tree
2019-11-22	Clifford Wolf	Merge pull request #1511 from YosysHQ/dave/always	commit \| commitdiff \| tree
2019-11-22	Marcin Kościelnicki	gowin: Remove show command from tests.	commit \| commitdiff \| tree
2019-11-22	Marcin Kościelnicki	gowin: Add missing .gitignore entries	commit \| commitdiff \| tree
2019-11-22	David Shah	Update CHANGELOG and README	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Another sloppy mistake!	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Merge remote-tracking branch 'origin/xaig_dff' into...	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	async2sync -> clk2fflogic	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	write_xaiger to not use module POs but only write outpu...	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	When expanding upwards, do not capture $__ABC9_{FF...	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	commit \| commitdiff \| tree
2019-11-22	Eddie Hung	Add test	commit \| commitdiff \| tree
2019-11-21	David Shah	sv: Add tests for SV always types	commit \| commitdiff \| tree
2019-11-21	David Shah	proc_dlatch: Add error handling for incorrect always_...	commit \| commitdiff \| tree
2019-11-21	David Shah	sv: Correct parsing of always_comb, always_ff and alway...	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Consistent log message, ignore 's' extension	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	endomain -> ctrldomain	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Add blackbox model for $__ABC9_FF_ so that clock partit...	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Add multi clock test	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Fix INIT values	commit \| commitdiff \| tree
2019-11-20	Clifford Wolf	Merge pull request #1507 from YosysHQ/clifford/verificfixes	commit \| commitdiff \| tree
2019-11-20	Clifford Wolf	Correctly treat empty modules as blackboxes in Verific	commit \| commitdiff \| tree
2019-11-20	Clifford Wolf	Do not rename VHDL entities to "entity(impl)" when...	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Add a equiv test too	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Add two tests	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	abc9 to support async flops $_DFF_[NP][NP][01]_	commit \| commitdiff \| tree
2019-11-20	Eddie Hung	Do not drop async control signals in abc_map.v	commit \| commitdiff \| tree
2019-11-19	Eddie Hung	Merge remote-tracking branch 'origin/master' into xaig_dff	commit \| commitdiff \| tree
2019-11-19	Clifford Wolf	Merge pull request #1449 from pepijndevos/gowin	commit \| commitdiff \| tree
2019-11-19	Pepijn de Vos	Remove dff init altogether	commit \| commitdiff \| tree
2019-11-19	Marcin Kościelnicki	Fix #1462, #1480.	commit \| commitdiff \| tree
2019-11-19	Marcin Kościelnicki	xilinx: Add simulation models for MULT18X18* and DSP48A*.	commit \| commitdiff \| tree
2019-11-18	Pepijn de Vos	add help for nowidelut and abc9 options	commit \| commitdiff \| tree
2019-11-18	Clifford Wolf	Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix	commit \| commitdiff \| tree
2019-11-18	whitequark	Merge pull request #1494 from whitequark/write_verilog...	commit \| commitdiff \| tree
2019-11-18	Marcin Kościelnicki	Fix #1496.	commit \| commitdiff \| tree
2019-11-18	whitequark	write_verilog: add -extmem option, to write split memor...	commit \| commitdiff \| tree
2019-11-17	Clifford Wolf	Merge pull request #1492 from YosysHQ/dave/wreduce...	commit \| commitdiff \| tree
2019-11-16	Pepijn de Vos	Merge branch 'master' of https://github.com/YosysHQ...	commit \| commitdiff \| tree
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