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yosys.git
2019-10-08
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-08
Eddie Hung
Revert "Add test that is expecting to fail"
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2019-10-08
Eddie Hung
Revert "Be mindful that sigmap(wire) could have dupes...
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2019-10-08
Eddie Hung
Merge pull request #1432 from YosysHQ/eddie/fix1427
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2019-10-08
Eddie Hung
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
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2019-10-08
Eddie Hung
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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2019-10-08
Eddie Hung
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
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2019-10-07
Eddie Hung
Cleanup
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2019-10-07
Eddie Hung
Rename $currQ to $abc9_currQ
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2019-10-07
Eddie Hung
Use "abc9_period" attribute for delay target
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2019-10-07
Eddie Hung
Get rid of latch_* in write_xaiger
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2019-10-07
Eddie Hung
Update comments in abc9_map.v
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2019-10-07
Eddie Hung
Remove -D_ABC9
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2019-10-07
Eddie Hung
Remove "write_xaiger -zinit"
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2019-10-07
Eddie Hung
Add comment on default flop init
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2019-10-07
Eddie Hung
Get rid of output_port lookup
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2019-10-06
Clifford Wolf
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_w...
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2019-10-06
Eddie Hung
Do not require changes to cells_sim.v; try and work...
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2019-10-05
Eddie Hung
Missing 'accept' at end of ice40_wrapcarry, spotted...
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2019-10-05
Clifford Wolf
Update README.md
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2019-10-05
Eddie Hung
Error if $currQ not found
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2019-10-05
Eddie Hung
Missed this
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2019-10-05
Eddie Hung
Add comment on why we have to match for clock-enable...
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2019-10-05
Eddie Hung
Add note on pattern detector
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2019-10-05
Miodrag Milanović
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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2019-10-05
Eddie Hung
Add comment on why partial multipliers are 18x18
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp_cascade
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2019-10-05
Eddie Hung
Improve comments for xilinx_dsp_CREG
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2019-10-05
Eddie Hung
Fix comment
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2019-10-05
Eddie Hung
Restore optimisation for sigM.empty()
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2019-10-05
Eddie Hung
Retry on fixing TODOs
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2019-10-05
Eddie Hung
Revert "Fix TODOs"
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2019-10-05
Eddie Hung
More comments, cleanup
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2019-10-05
Eddie Hung
Fix TODOs
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2019-10-05
Eddie Hung
Consistency
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp
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2019-10-05
Eddie Hung
Fix typo in check_label()
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2019-10-05
Eddie Hung
abc -> abc9
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2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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2019-10-05
Eddie Hung
Fix from merge
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2019-10-05
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-05
Eddie Hung
Add temporary `abc9 -nomfs` and use for `synth_xilinx...
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2019-10-05
Eddie Hung
Use read_args for read_verilog
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2019-10-05
Eddie Hung
Remove DSP48E1 from *_cells_xtra.v
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2019-10-05
Eddie Hung
Fix merge issues
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2019-10-04
Eddie Hung
Merge remote-tracking branch 'origin/eddie/abc_to_abc9...
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2019-10-04
Eddie Hung
Fix xilinx_dsp for unsigned extensions
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2019-10-04
Eddie Hung
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true...
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2019-10-04
Eddie Hung
Add Const::{begin,end,empty}()
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2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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2019-10-04
Eddie Hung
Panic over. Model was elsewhere. Re-arrange for consistency
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2019-10-04
Eddie Hung
Oops
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2019-10-04
Eddie Hung
Ohmilord this wasn't added all this time!?!
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2019-10-04
Eddie Hung
Add -async2sync to help text as per @daveshah1
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2019-10-04
Miodrag Milanovic
Fixes for MSVC build
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2019-10-03
Eddie Hung
Use `sat -tempinduct` and comments for why equiv_opt...
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2019-10-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-03
Eddie Hung
Restore part of doc
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2019-10-03
Eddie Hung
Disable equiv check for ice40 latches
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2019-10-03
Eddie Hung
Add new -async2sync option
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2019-10-03
Eddie Hung
Use equiv_opt -async2sync for xilinx
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2019-10-03
Eddie Hung
English
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2019-10-03
Eddie Hung
Revert "equiv_opt to call async2sync when not -multiclo...
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2019-10-03
Eddie Hung
Revert "Update doc for equiv_opt"
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2019-10-03
Clifford Wolf
Change smtbmc "Warmup failed" status to "PREUNSAT"
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2019-10-03
Clifford Wolf
Update ABC to git rev 623b5e8
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2019-10-03
Clifford Wolf
Bump version
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2019-10-03
Clifford Wolf
Merge pull request #1419 from YosysHQ/eddie/lazy_derive
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2019-10-03
Clifford Wolf
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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2019-10-03
Clifford Wolf
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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2019-10-03
Clifford Wolf
Add "check -allow-tbuf"
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2019-10-03
David Shah
Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16
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2019-10-03
Eddie Hung
Fix broken CI, check reset even for constants, trim...
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2019-10-03
Eddie Hung
Merge pull request #1423 from YosysHQ/eddie/techmap_rep...
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2019-10-03
Eddie Hung
Fix test
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2019-10-03
Eddie Hung
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
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2019-10-03
Eddie Hung
Update test
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2019-10-03
Eddie Hung
Refactor peepopt_dffmux and be sensitive to \init when...
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2019-10-03
Eddie Hung
Add test
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2019-10-03
Eddie Hung
log_dump() to support State enum
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2019-10-02
Eddie Hung
Be mindful that sigmap(wire) could have dupes when...
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2019-10-02
Eddie Hung
Add test that is expecting to fail
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2019-10-02
Eddie Hung
Also rename cells with _TECHMAP_REPLACE_. prefix, as...
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2019-10-02
Eddie Hung
Extend test with renaming cells with prefix too
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2019-10-02
Clifford Wolf
Merge pull request #1428 from YosysHQ/clifford/fixbtor
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2019-10-02
Clifford Wolf
Add "check -mapped"
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2019-10-02
Clifford Wolf
Fix btor back-end to use "state" instead of "input...
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2019-10-01
Eddie Hung
More fixes
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2019-10-01
Eddie Hung
Escape Verilog identifiers for legality outside of...
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2019-10-01
Miodrag Milanović
Merge pull request #1426 from YosysHQ/mmicko/fix_environ
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2019-10-01
Miodrag Milanovic
Define environ, fixes #1424
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2019-10-01
David Shah
ecp5: Fix shuffle_enable port
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2019-10-01
David Shah
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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2019-10-01
Eddie Hung
Add test
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2019-10-01
Eddie Hung
techmap wires named _TECHMAP_REPLACE_.<identifier>...
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2019-10-01
Eddie Hung
No need to punch ports at all
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2019-09-30
Eddie Hung
Resolve FIXME on calling proc just once
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2019-09-30
Eddie Hung
Cleanup $currQ from aigerparse
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2019-09-30
Eddie Hung
Remove need for $currQ port connection
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2019-09-30
Eddie Hung
Add explanation to abc_map.v
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