yosys.git
2014-12-19 Clifford WolfFixed another bug in write_blif handling of $lut cells
2014-12-17 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-12-17 Clifford WolfFixed writing of $lut cells in BLIF backend
2014-12-16 Clifford WolfFixed build with gcc 4.6
2014-12-14 Clifford WolfAdded "write_blif -undef" and support for special ...
2014-12-14 Clifford WolfAdded "write_blif -blackbox"
2014-12-14 Clifford WolfAdded "blif -unbuf" feature
2014-12-14 Clifford WolfRemoved psmisc from deps list (usually fuser is already...
2014-12-12 Clifford WolfAdded psmisc to prerequisites
2014-12-12 Clifford WolfRemoved UTF-8 chars from techmap.v
2014-12-12 Clifford WolfAdded missing prerequisites to README
2014-12-11 Clifford WolfAdded IdString::destruct_guard hack
2014-12-11 Clifford WolfCompile fix for visual studio
2014-12-11 Clifford WolfFixed supply0/supply1 with many wires
2014-12-08 Clifford WolfAdded functionality to dff2dffe pass
2014-12-08 Clifford WolfAdded bool constructors to SigBit and SigSpec
2014-12-08 Clifford WolfAdded module->addDffe() and module->addDffeGate()
2014-12-08 Clifford WolfAdded skeleton dff2dffe pass
2014-12-08 Clifford WolfAdded more documentation fixmes for nontrivial register...
2014-12-08 Clifford WolfAdded $dffe cell type
2014-12-08 Clifford WolfAdded $_DFFE_??_ cell types
2014-12-07 Clifford WolfMerge branch 'master' of https://github.com/Martoni...
2014-12-07 Fabien Marteaumanual/presentation.tex: bg option is unknown with...
2014-12-06 Clifford WolfMerge pull request #43 from Martoni/master
2014-12-05 Fabien Marteausuppressing semi-colon at the end of dot files
2014-12-04 Clifford WolfAdded some missing .gitignore in manual/
2014-11-27 Clifford WolfFixed bug in "hierarchy -top" with array of instances
2014-11-24 Clifford WolfFixed minor bug in parsing delays
2014-11-24 Clifford WolfFixed two minor bugs in constant parsing
2014-11-24 Clifford WolfSome fixes in stubnets example
2014-11-20 Clifford WolfMerge pull request #42 from slowriot/master
2014-11-20 SlowRiotswitching from unreliable typedefs to precisely sized...
2014-11-20 SlowRiotfixing incorrect buffer size allocation, and unsafe...
2014-11-14 Clifford WolfAdded warning for use of 'z' constants in HDL
2014-11-12 Clifford WolfFixed parsing of nested verilog concatenation and replicate
2014-11-12 Clifford WolfAnother 'make vcxsrc'
2014-11-11 Clifford WolfSome fixed in "make vcxsrc" srcfiles.txt creation
2014-11-11 Clifford WolfSplit MXE "make dist" into MXE "make mxebin" and non...
2014-11-09 Clifford WolfAdded "yosys -qq" to also quiet warning messages
2014-11-09 Clifford WolfIntroducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NOR...
2014-11-09 Clifford WolfAdded log_warning() API
2014-11-08 Clifford WolfAdded automatic "make clean" to abc "hg pull" make...
2014-11-08 Clifford WolfSome fixes in presentation
2014-11-08 Clifford WolfAdded missing fixup_ports() calls to "rename" command
2014-11-08 Clifford WolfUse a cache for log_id() memory management
2014-11-08 Clifford WolfNow we are in Yoys 0.4+ development
2014-11-08 Clifford WolfYosys 0.4 yosys-0.4
2014-11-08 Clifford WolfAdded "ENABLE_PLUGINS := 0" to verific amd64 build...
2014-11-08 Clifford WolfVarious documentation updates
2014-11-08 Clifford WolfAdded "Nx" syntax to "show" command for repeating SigChunks
2014-11-07 Clifford WolfAdded "used" attribute to entries in yosys_cover_list
2014-11-07 Clifford WolfMinor corrections in CodingReadme
2014-11-07 Clifford WolfImproved TopoSort determinism
2014-11-07 Clifford WolfFixed generation of temp names in verilog backend
2014-11-07 Clifford WolfUpdated ABC to 5b5af75f1dda
2014-11-07 Clifford WolfChangelog for Yosys 0.4
2014-11-07 Clifford WolfFixed typo in "log_cmd_error_exception"
2014-11-06 Clifford WolfMade "cover" a compile-time option (disabled by default)
2014-11-05 Clifford WolfRemoved QMAKE variable from Makefile
2014-10-31 Clifford WolfAdded "abc" label in synth script
2014-10-31 Clifford WolfAdded "opt -full" alias for all more aggressive optimiz...
2014-10-30 Clifford WolfFixed parsing of "module mymod #( parameter foo = 1...
2014-10-30 Clifford WolfImproved nomem2reg documentation
2014-10-29 Clifford WolfAdded support for empty lines to here documents
2014-10-29 Clifford WolfAST simplifier: optimize constant AST_CASE nodes before...
2014-10-27 Clifford WolfAdded support for task and function args in parentheses
2014-10-26 Clifford WolfImprovements in $readmem[bh] implementation
2014-10-26 Clifford WolfAdded support for $readmemh/$readmemb
2014-10-25 Clifford WolfFixed constant "cond ? string1 : string2" with strings...
2014-10-23 Clifford WolfRe-introduced Yosys::readsome() helper function
2014-10-19 Clifford Wolfminor indenting corrections
2014-10-19 Clifford WolfMerge pull request #40 from parvizp/compile_mac_10.9.2
2014-10-19 Parviz PalangpourBuilds on Mac 10.9.2 with LLVM 3.5.
2014-10-18 Clifford WolfImproved new_id() for win32
2014-10-18 Clifford WolfAlso look for yosys-abc in parent dir on win32
2014-10-18 Clifford WolfVarious improvements to version reporting on win32
2014-10-18 Clifford WolfDisabled READLINE in MXE cross build
2014-10-18 Clifford WolfFixed typo in test_cell
2014-10-18 Clifford WolfFixed shell prompt and proc_self_dirname() for win32
2014-10-18 Clifford WolfFixed various VS warnings
2014-10-18 Clifford WolfCreate vcxsrc in mxe build "make dist"
2014-10-18 Clifford WolfMoved yosys-config.in to misc/
2014-10-17 Clifford WolfAdded notes regarding building in VS
2014-10-17 Clifford WolfAdded vcxproj_files.txt to MXE "make dist"
2014-10-17 Clifford WolfMore win32 (mxe and vs) build fixes
2014-10-17 Clifford WolfVarious win32 / vs build fixes
2014-10-17 Clifford WolfAdded genfiles.zip to MXE "make dist"
2014-10-17 Clifford WolfVarious MXE build fixes
2014-10-17 William SpeirsHeader changes so it will compile on VS
2014-10-17 William SpeirsWrapped math in int constructor
2014-10-17 Clifford WolfFixed a few VS warnings
2014-10-16 Clifford WolfDon't be too smart with $dff cells with "init" attribut...
2014-10-16 Clifford WolfSome cleanups in opt_clean
2014-10-16 Clifford WolfPrint "SystemVerilog" in "read_verilog -sv" log messages
2014-10-15 Clifford WolfFixed RTLIL::SigSpec::parse() for out-of-range bit...
2014-10-15 Clifford WolfFixed handling of invalid array access in mem2reg code
2014-10-15 Clifford WolfReplaced log_assert() do { ... } while (0) hack with...
2014-10-15 Clifford WolfFixed gcc warning
2014-10-15 Clifford WolfFixed MXE build
2014-10-14 Clifford WolfMerge branch 'win32'
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