| 2019-01-18 |
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once. |
commit | commitdiff | tree |
| 2019-01-17 |
Alain Péteut | cli: add missing default for `generate` |
commit | commitdiff | tree |
| 2019-01-17 |
whitequark | lib.fifo: add basic formal specification. |
commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.ast: allow sampling ClockSignal, ResetSignal. |
commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell. |
commit | commitdiff | tree |
| 2019-01-17 |
whitequark | formal: extract from toplevel module. |
commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer. |
commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.ast: add Sample. |
commit | commitdiff | tree |
| 2019-01-16 |
whitequark | lib.fifo: port sync FIFO queues from Migen. |
commit | commitdiff | tree |
| 2019-01-16 |
whitequark | hdl.ast: fix naming of Signal.like() signals when trace... |
commit | commitdiff | tree |
| 2019-01-16 |
whitequark | back.rtlil: slightly nicer naming for $next signals... |
commit | commitdiff | tree |
| 2019-01-16 |
whitequark | back.rtlil: rename \sig$next to $next$sig. |
commit | commitdiff | tree |
| 2019-01-16 |
whitequark | Travis: install SymbiYosys and Yices2. |
commit | commitdiff | tree |
| 2019-01-15 |
whitequark | Unbreak 655d02d5. |
commit | commitdiff | tree |
| 2019-01-15 |
William D.... | back.rtlil: Generate $anyconst and $anyseq cells. |
commit | commitdiff | tree |
| 2019-01-15 |
William D.... | hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method... |
commit | commitdiff | tree |
| 2019-01-15 |
William D.... | hdl.ast: Add AnyConst and AnySeq value types. |
commit | commitdiff | tree |
| 2019-01-15 |
Sebastien Bourdeauducq | README: add LambdaConcept sponsorship |
commit | commitdiff | tree |
| 2019-01-14 |
whitequark | lib.io: pass pin to platform.get_tristate(). |
commit | commitdiff | tree |
| 2019-01-14 |
whitequark | hdl.ir: allow explicitly requesting flattening. |
commit | commitdiff | tree |
| 2019-01-14 |
whitequark | lib.io: lower to platform-independent tristate buffer. |
commit | commitdiff | tree |
| 2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS. |
commit | commitdiff | tree |
| 2019-01-13 |
whitequark | hdl.dsl: cases wider than switch test value are unreach... |
commit | commitdiff | tree |
| 2019-01-13 |
whitequark | hdl.dsl: accept (but warn on) cases wider than switch... |
commit | commitdiff | tree |
| 2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals. |
commit | commitdiff | tree |
| 2019-01-13 |
whitequark | back.verilog: better error message if Yosys is not... |
commit | commitdiff | tree |
| 2019-01-08 |
whitequark | back.verilog: remove undriven check. |
commit | commitdiff | tree |
| 2019-01-06 |
Adam Greig | Give the top level scope a name to fix VCD hierarchy. |
commit | commitdiff | tree |
| 2019-01-02 |
whitequark | hdl.ast: allow slicing [n:n] into n-bit value. |
commit | commitdiff | tree |
| 2019-01-02 |
whitequark | back.rtlil: translate empty slices correctly. |
commit | commitdiff | tree |
| 2019-01-02 |
William D.... | back.rtlil: Generate RTLIL for Assert/Assume statements. |
commit | commitdiff | tree |
| 2019-01-02 |
William D.... | hdl.xfrm: Add Assert and Assume abstract methods for... |
commit | commitdiff | tree |
| 2019-01-02 |
William D.... | hdl.dsl: Support Assert and Assume where an Assign... |
commit | commitdiff | tree |
| 2019-01-02 |
William D.... | hdl.ast: Add Assert and Assign statements. |
commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.ast: experimentally add Value._as_const. |
commit | commitdiff | tree |
| 2019-01-01 |
whitequark | back.rtlil: fix typo. |
commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.rec: include record name in error message. |
commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.rec: use a helpful error on unknown field reference. |
commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.mem: add DummyPort, for testing and verification. |
commit | commitdiff | tree |
| 2018-12-31 |
whitequark | back.rtlil: match shape of Array elements to ArrayProxy... |
commit | commitdiff | tree |
| 2018-12-31 |
whitequark | back.rtlil: fix typo. |
commit | commitdiff | tree |
| 2018-12-29 |
whitequark | lib.cdc: fix tests to actually run. |
commit | commitdiff | tree |
| 2018-12-29 |
whitequark | back.pysim: warn if simulation is not run. |
commit | commitdiff | tree |
| 2018-12-28 |
whitequark | hdl.rec: add basic record support. |
commit | commitdiff | tree |
| 2018-12-28 |
whitequark | tracer: factor out get_src_loc(). |
commit | commitdiff | tree |
| 2018-12-27 |
whitequark | lib.coding: fix tests to actually run, and fix code... |
commit | commitdiff | tree |
| 2018-12-27 |
whitequark | hdl.dsl: add support for fsm.ongoing(). |
commit | commitdiff | tree |
| 2018-12-27 |
whitequark | hdl.mem: add missing __all__. |
commit | commitdiff | tree |
| 2018-12-26 |
Jean-François... | compat.genlib.coding: fix import. |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | lib.coding: port from Migen. |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | lib.cdc: add tests for MultiReg. |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: forbid m.next= inside of FSM but outside of... |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: provide generated values for FSMs. |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.ir: add an API for retrieving generated values... |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | examples: add an FSM usage example (UART receiver). |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: add signal decoder to FSM state signal. |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: implement FSM. |
commit | commitdiff | tree |
| 2018-12-26 |
whitequark | back.rtlil: clarify $verilog_initial_trigger behavior... |
commit | commitdiff | tree |
| 2018-12-24 |
whitequark | back.rtlil: unbreak d47c1f8a. |
commit | commitdiff | tree |
| 2018-12-24 |
whitequark | hdl.mem: allow omitting memory simulation logic. |
commit | commitdiff | tree |
| 2018-12-24 |
whitequark | back.rtlil: use one $meminit cell, not one per word. |
commit | commitdiff | tree |
| 2018-12-24 |
whitequark | hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. |
commit | commitdiff | tree |
| 2018-12-24 |
whitequark | hdl.xfrm: implement SwitchCleaner, for pruning empty... |
commit | commitdiff | tree |
| 2018-12-24 |
whitequark | back.rtlil: always output negative values as two's... |
commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: emit dummy logic to work around Verilog... |
commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: do not translate empty fragments. |
commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: only translate switch tests once. |
commit | commitdiff | tree |
| 2018-12-23 |
whitequark | cli: generate: guess file type from extension. |
commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: fix swapped operands in mux codegen. |
commit | commitdiff | tree |
| 2018-12-23 |
whitequark | cli: new module, for basic design generaton/simulation. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: avoid cycles in union-find graph in LHSGroupA... |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat.genlib.fsm: fix naming for non-Signal LHS. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: flatten hierarchy based on memory accesses... |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: factor out _merge_subfragment. NFC. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: split processes as finely as possible. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: remove useless condition. NFC. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: implement LHSGroupAnalyzer. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: always initialize the entire memory. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: use nicer names for next_value/next_value_ce... |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.mem: allow changing init value after creating memory. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.verilog: do not rename internal signals. |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: fix confusing naming for memory port address... |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: fix port propagation between siblings, in the... |
commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: do not finalize native submodules twice. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: use more informative signal naming for ports. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: fix port propagation between siblings. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | compat: provide verilog.convert shim. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: do not flatten instances or collect ports from... |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | compat: provide Memory shim. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: ensure transparent read port model has correct... |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.pysim: give numeric names to unnamed subfragments... |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: use different naming for array signals. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: add simulation model for memory. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.pysim: fix an issue with too few funclet slots. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: add tests for all error conditions. |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: tie rdport.en high for asynchronous or transpa... |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.rtlil: more consistent prefixing for subfragment... |
commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: correctly handle named output and inout ports. |
commit | commitdiff | tree |
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projects / nmigen.git / shortlog