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gram.git
2022-07-23 Cesar StraussMerge runsimsoc2.sh into runsimsoc.sh commit | commitdiff | tree
2022-04-15 Luke Kenneth... remove pyvcd dependency, it is pulled in by nmigen... commit | commitdiff | tree
2022-04-15 Luke Kenneth... add features option to gramCore and PHY wishbone buses... commit | commitdiff | tree
2022-04-15 Luke Kenneth... fix reset to be xdr=4x in ECP5DDRPHY commit | commitdiff | tree
2022-04-15 Luke Kenneth... connect (new) reset signal on IOPads which comes from... commit | commitdiff | tree
2022-04-14 Luke Kenneth... whilst IOpads and PLLs were driving from dramsync,... commit | commitdiff | tree
2022-04-10 Raptor Engineering... Don't reset the core / peripherals on DRAM controller... commit | commitdiff | tree
2022-04-10 Raptor Engineering... Put sysclk2x back under system reset control commit | commitdiff | tree
2022-04-09 Raptor Engineering... Avoid timing violation on ECP5 PHY PAUSE signal commit | commitdiff | tree
2022-04-09 Raptor Engineering... Revert "Avoid timing violation on ECP5 PHY PAUSE signal" commit | commitdiff | tree
2022-04-09 Raptor Engineering... Avoid timing violation on ECP5 PHY PAUSE signal commit | commitdiff | tree
2022-04-09 Raptor Engineering... Wire up missing CRG / DDR3 clock control / reset signals commit | commitdiff | tree
2022-04-07 Raptor Engineering... Re-apply part of 180026c72f0e1d3ef365b2214288d4a543a238dd commit | commitdiff | tree
2022-04-07 Raptor Engineering... Backport litedram 05ed5bf59d31029d3f91c5a348cdd539a150631b commit | commitdiff | tree
2022-04-07 Raptor Engineering... Working at 50MHz system clock commit | commitdiff | tree
2022-04-07 Raptor Engineering... Switch CRG back over to ECP5 version commit | commitdiff | tree
2022-04-07 Raptor Engineering... Partially revert GIT hash 180026c72f0e1d3ef365b2214288d... commit | commitdiff | tree
2022-04-07 Raptor Engineering... Properly connect reset and cs signals commit | commitdiff | tree
2022-04-07 Raptor Engineering... Add initial support for external DRAM init on the Rapto... commit | commitdiff | tree
2022-03-17 Luke Kenneth... initialise bitslip with a specific value rather than... commit | commitdiff | tree
2022-03-17 Luke Kenneth... add alternative variant of runsimsoc.sh commit | commitdiff | tree
2022-03-13 Luke Kenneth... add 1024M_ddr3_parameters.vh for MT41K64M16 commit | commitdiff | tree
2022-03-11 Luke Kenneth... add a 2nd clock, this one deliberately the commit | commitdiff | tree
2022-03-11 Luke Kenneth... annoyingly reverting reset_n naming back to reset commit | commitdiff | tree
2022-03-10 Luke Kenneth... tidyup on gramWishbone class, add comments commit | commitdiff | tree
2022-03-10 Luke Kenneth... tidy up gramWishbone constructor, pass Wishbone feature... commit | commitdiff | tree
2022-03-10 Luke Kenneth... code-cleanup and copyright notices commit | commitdiff | tree
2022-03-01 Luke Kenneth... fix up simulation to be more like VERSA_ECP5 commit | commitdiff | tree
2022-02-28 Luke Kenneth... remove unneeded import commit | commitdiff | tree
2022-02-26 Luke Kenneth... use dict for lookup of DFI to pads names commit | commitdiff | tree
2022-02-26 Luke Kenneth... add missing reset-HI values to cas_n, cs_n, we_n and... commit | commitdiff | tree
2022-02-25 Luke Kenneth... get chipselect (cs_n) name right in ECP5DDRPHY commit | commitdiff | tree
2022-02-25 Luke Kenneth... restore naming convention "cs_r" on DFI Interface commit | commitdiff | tree
2022-02-25 Luke Kenneth... set name of DFI interface to ecp5phy in ECP5DDRPHY commit | commitdiff | tree
2022-02-25 Luke Kenneth... allow DDR3 reset (rst) signal to be controlled by DFI... commit | commitdiff | tree
2022-02-24 Luke Kenneth... add a BitSlip module commit | commitdiff | tree
2022-02-24 Luke Kenneth... replace the simulation Clock-Reset-Generator with one... commit | commitdiff | tree
2022-02-24 Luke Kenneth... add CSRs to FakePHY which allows at least testing of... commit | commitdiff | tree
2022-02-22 Luke Kenneth... remove continue/skip and add comment that all commit | commitdiff | tree
2022-02-21 Luke Kenneth... add debug print statements to investigate FakePHY commit | commitdiff | tree
2022-02-21 Luke Kenneth... add a debug verilog dump of one of the FakePHY SocTest... commit | commitdiff | tree
2022-02-20 Luke Kenneth... add dfii submodules so they get explicit names commit | commitdiff | tree
2022-02-20 Luke Kenneth... add name to DFI Interface (helps gtkwave traces) commit | commitdiff | tree
2022-02-19 Luke Kenneth... fix gram unit test imports commit | commitdiff | tree
2022-02-16 Luke Kenneth... fix ECP5DDRPHY cs declaration commit | commitdiff | tree
2020-08-07 Jean THOMASgram.test.test_core_bankmachine: Reduce formal test... commit | commitdiff | tree
2020-08-07 Jean THOMASAdd links to other memory controller projects commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.multiplexer: Fix variable name in _Steerer commit | commitdiff | tree
2020-08-07 Jean THOMASgram.test.test_core_multiplexer: Add test for _Steerer... commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.multiplexer: Remove unnecessary array slicing commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.multiplexer: Code cleaning in _Steerer commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.multiplexer: Cleaner code in _Steerer commit | commitdiff | tree
2020-08-07 Jean THOMASexamples: Display rdly map commit | commitdiff | tree
2020-08-07 Jean THOMASgram.test.test_core_bankmachine: Ensure refresh_gnt... commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.bankmachine: Make condition code cleaner commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.bankmachine: Add comment for address slicers commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.bankmachine: Remove unused local variables... commit | commitdiff | tree
2020-08-07 Jean THOMASgram.core.bankmachine: Rename LiteDRAM -> gram in docum... commit | commitdiff | tree
2020-08-07 Jean THOMASgram.test.test_core_bankmachine: Add test for _AddressS... commit | commitdiff | tree
2020-08-07 Jean THOMASgram.test.test_core_refresher: Add test for ZQCSExecute... commit | commitdiff | tree
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Fix ECP5DDRPHYInit (wrong domains) commit | commitdiff | tree
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Remove internal signal for delay commit | commitdiff | tree
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Detect burstdet on rising edge... commit | commitdiff | tree
2020-08-06 Jean THOMASexamples: Load stock calibration profile if calibration... commit | commitdiff | tree
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Make non-critical signals reset... commit | commitdiff | tree
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Revert to LiteDRAM's dqs_re commit | commitdiff | tree
2020-08-06 Jean THOMASgram.core.multiplexer: Fix regression introduced in... commit | commitdiff | tree
2020-08-06 Jean THOMASexamples: Make frequency a parameter commit | commitdiff | tree
2020-08-06 Jean THOMASexamples: Continue self-test even if calibration is... commit | commitdiff | tree
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Remove unused stream import commit | commitdiff | tree
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Add documentation for _DQSBUFMSett... commit | commitdiff | tree
2020-08-06 Jean THOMASgram.test: Use correct timing for simulations commit | commitdiff | tree
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Fix DQSBUFM's pause signal (fixes... commit | commitdiff | tree
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Code cleaning commit | commitdiff | tree
2020-08-05 Jean THOMASgram.core.bankmachine: Factorize tXXDController valid... commit | commitdiff | tree
2020-08-05 Jean THOMASFix code styling commit | commitdiff | tree
2020-08-05 Jean THOMASRemove steerer_sel function commit | commitdiff | tree
2020-08-05 Jean THOMASFix test using delays for comb propagation instead... commit | commitdiff | tree
2020-08-05 Jean THOMASAdd unit test for tXXDController commit | commitdiff | tree
2020-08-04 Jean THOMASFix AntiStarvation test commit | commitdiff | tree
2020-08-04 Jean THOMASFix exception condition commit | commitdiff | tree
2020-08-04 Jean THOMASRaise ValueError if the number of DQ pads is not a... commit | commitdiff | tree
2020-08-04 Jean THOMASRaise ValueError if RefreshTimer period is unsupported... commit | commitdiff | tree
2020-08-04 Jean THOMASRaise ValueError if anti-starvation timeout is unsuppor... commit | commitdiff | tree
2020-08-04 Jean THOMASRaise ValueError if commands array isn't of len=4 ... commit | commitdiff | tree
2020-08-04 Jean THOMASSample data based on datavalid signal (fixes #47) commit | commitdiff | tree
2020-08-04 Jean THOMASRaise exception if no native port is present (fixing... commit | commitdiff | tree
2020-08-04 Jean THOMASMake burstdet_reg reset-less commit | commitdiff | tree
2020-08-04 Jean THOMASFix simulation to support diff pairs commit | commitdiff | tree
2020-08-04 Jean THOMASFix sel signal used in wishbone frontend commit | commitdiff | tree
2020-08-04 Jean THOMASDefault SEL to 1's if SEL=0 (fixes #43) commit | commitdiff | tree
2020-08-04 Jean THOMASRemove unused variable in wishbone frontend test commit | commitdiff | tree
2020-08-03 Jean THOMASAdd additional tests for sel signal commit | commitdiff | tree
2020-08-03 Jean THOMASAdd more sel tests commit | commitdiff | tree
2020-08-03 Jean THOMASFix native port we signal (fixes #44) commit | commitdiff | tree
2020-08-03 Jean THOMASFix sel test commit | commitdiff | tree
2020-08-03 Jean THOMASAdd test for wishbone sel signal commit | commitdiff | tree
2020-08-03 Jean THOMASRevert to dqs_re from LiteDRAM commit | commitdiff | tree
2020-08-03 Jean THOMASUse const qualifier for gram_read/gram_write commit | commitdiff | tree
2020-08-03 Jean THOMASUpdate setup.py (based on LUNA) commit | commitdiff | tree
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