2014-03-11 |
Siesh1oo | Rebase to cliffordwolf repo HEAD finished. |
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2014-03-11 |
Siesh1oo | - Makefile: include $(PWD) in PATH, since 'make test... |
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2014-03-11 |
Siesh1oo | - Makefile: fix typo in LDFLAGS: obviously -L, not... |
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2014-03-11 |
Siesh1oo | - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and... |
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2014-03-11 |
Siesh1oo | - Makefile: resolve merge conflict. |
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2014-03-11 |
Clifford Wolf | OSX compatible creation of stdcells.inc, using code... |
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2014-03-11 |
Clifford Wolf | Merged addition of SED makefile variable from github... |
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2014-03-11 |
Clifford Wolf | Merged a few fixes for non-posix systems from github... |
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2014-03-11 |
Clifford Wolf | Added support for `line compiler directive |
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2014-03-11 |
Siesh1oo | - passes/techmap/Makefile.inc: POSIX 'od' has no ... |
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2014-03-11 |
Clifford Wolf | Fixed memory corruption in passes/abc/blifparse.cc |
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2014-03-11 |
Clifford Wolf | Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh |
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2014-03-11 |
Clifford Wolf | Use "verilog -noattr" in tests/techmap/mem_simple_4x1... |
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2014-03-10 |
Siesh1oo | - Makefile: include $(PWD) in PATH, since 'make test... |
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2014-03-10 |
Siesh1oo | - libs/ezsat/ezminisat.cc: use sigemptyset() to clear... |
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2014-03-10 |
Siesh1oo | - Makefile: fix typo in LDFLAGS: obviously -L, not... |
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2014-03-10 |
Siesh1oo | - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and... |
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2014-03-10 |
Siesh1oo | - frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc... |
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2014-03-10 |
Siesh1oo | - Makefile, techlibs/common/Makefile.inc: call GNU... |
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2014-03-10 |
Siesh1oo | - libs/ezsat/ezminisat.cc: use POSIX.2001 sigaction... |
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2014-03-10 |
Siesh1oo | - Makefile, kernel/posix_compatibility.h/.cc: provide... |
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2014-03-10 |
Siesh1oo | - README: fix typo in sed-command for minisat-include... |
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2014-03-10 |
Siesh1oo | - frontends/vhdl2verilog/vhdl2verilog.cc: #include... |
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2014-03-10 |
Siesh1oo | - kernel/register.cc: need to #include <cerrno> or... |
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2014-03-10 |
Siesh1oo | - kernel/driver.cc: need to #include <cerrno> or errno... |
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2014-03-10 |
Siesh1oo | - kernel/log.h: add rusage()-based fallback for system... |
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2014-03-10 |
Siesh1oo | - libs/ezsat/ezsat.cc: need to #include <cmath> or... |
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2014-03-10 |
Siesh1oo | - passes/abc/abc.cc: #include <cerrno> for errno;... |
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2014-03-10 |
Siesh1oo | - passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode... |
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2014-03-10 |
Clifford Wolf | Fixed a typo in RTLIL::Module::addReduce... |
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2014-03-10 |
Clifford Wolf | Improved verific command (added support for some operators) |
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2014-03-10 |
Clifford Wolf | Improvements in verific command |
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2014-03-10 |
Clifford Wolf | Added RTLIL::Module::add... helper methods |
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2014-03-09 |
Clifford Wolf | Added "verific" command |
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2014-03-09 |
Clifford Wolf | Fixed dumping of timing() { .. } block in libparse |
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2014-03-09 |
Clifford Wolf | Verbose reading of liberty and constr files in ABC... |
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2014-03-07 |
Clifford Wolf | Fixed bug in freduce command |
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2014-03-07 |
Clifford Wolf | Some minor code cleanups in freduce command |
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2014-03-07 |
Clifford Wolf | Bugfix in ilang frontend autoidx recovery |
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2014-03-07 |
Clifford Wolf | Use log_abort() and log_assert() in BTOR backend |
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2014-03-06 |
Clifford Wolf | Added freduce -dump |
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2014-03-06 |
Clifford Wolf | Added freduce -stop |
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2014-03-06 |
Clifford Wolf | Fixed gcc compiler warning |
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2014-03-06 |
Clifford Wolf | Fixed undef handling in opt_reduce |
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2014-03-06 |
Clifford Wolf | Fixes for improved techmap of shifts with large B inputs |
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2014-03-06 |
Clifford Wolf | Fixed use of frozen literals in SatGen |
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2014-03-06 |
Clifford Wolf | Strictly zero-extend unsigned A-inputs of shift operati... |
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2014-03-06 |
Clifford Wolf | Added techmap -max_iter option |
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2014-03-06 |
Clifford Wolf | Improved techmap of shift with wide B inputs |
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2014-03-06 |
Clifford Wolf | Strictly zero-extend unsigned A-inputs of shift operations |
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2014-03-05 |
Clifford Wolf | Switched to EZMINISAT_SIMPSOLVER as default SAT solver |
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2014-03-05 |
Clifford Wolf | Include id2ast pointers when dumping AST |
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2014-03-05 |
Clifford Wolf | Fixed merging of compatible wire decls in AST frontend |
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2014-03-05 |
Clifford Wolf | Bugfix in recursive AST simplification |
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2014-03-03 |
Clifford Wolf | fixed freduce for Minisat::SimpSolver: use frozen_literal() |
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2014-03-03 |
Clifford Wolf | ezSAT: Added frozen_literal() API |
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2014-03-03 |
Clifford Wolf | ezSAT: Fixed handling of eliminated Literals, added... |
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2014-03-01 |
Clifford Wolf | Added ezSAT::eliminated API to help the SAT solver... |
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2014-03-01 |
Clifford Wolf | ezSAT bugfix: don't call virtual methods in base class... |
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2014-03-01 |
Clifford Wolf | Removed ezSAT::assumed() API |
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2014-03-01 |
Clifford Wolf | Removed ezSAT built-in brute-froce solver |
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2014-03-01 |
Clifford Wolf | Fixed vhdl2verilog temp dir name |
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2014-03-01 |
Clifford Wolf | Fixed vhdl2verilog help message |
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2014-02-27 |
Clifford Wolf | Fixed const folding of $bu0 cells |
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2014-02-26 |
Clifford Wolf | Fixed bit-extending in $mux argument (use $bu0 instead... |
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2014-02-26 |
Clifford Wolf | Added support for $bu0 to SatGen |
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2014-02-24 |
Clifford Wolf | Don't blow up constants unneccessarily in Verilog frontend |
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2014-02-23 |
Clifford Wolf | Added support for Minisat::SimpSolver + ezSAT frezze... |
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2014-02-23 |
Clifford Wolf | Fixed small memory leak in Pass::call() |
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2014-02-22 |
Clifford Wolf | Fixed bug in generation of undefs for $memwr MUXes |
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2014-02-22 |
Clifford Wolf | Fixed bug (typo) in passes/opt/opt_const.cc |
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2014-02-22 |
Clifford Wolf | Added $lut support to blif backend (by user eddiehung... |
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2014-02-22 |
Clifford Wolf | Added ezMiniSat EZMINISAT_INCREMENTAL compile-time... |
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2014-02-22 |
Clifford Wolf | Made MiniSat solver backend configurable in ezminisat.h |
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2014-02-21 |
Clifford Wolf | Added workaround for vhdl-style edge triggers from... |
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2014-02-21 |
Clifford Wolf | Added vhdl2verilog |
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2014-02-21 |
Clifford Wolf | Progress in presentation |
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2014-02-21 |
Clifford Wolf | Better handling of nameDef and nameRef in edif backend |
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2014-02-21 |
Clifford Wolf | Fixed instantiating multi-bit ports in edif backend |
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2014-02-21 |
Clifford Wolf | Use private namespace in mem_simple_4x1_map |
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2014-02-21 |
Clifford Wolf | Added tests/techmap/mem_simple_4x1 |
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2014-02-21 |
Clifford Wolf | Renamed "write_blif -subckt" to "write_blif -icells... |
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2014-02-21 |
Clifford Wolf | Progress in presentation |
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2014-02-20 |
Clifford Wolf | Progress in presentation |
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2014-02-20 |
Clifford Wolf | Added _TECHMAP_REPLACE_ feature to techmap |
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2014-02-20 |
Clifford Wolf | Added "extract -ignore_parameters" and "extract -ignore... |
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2014-02-20 |
Clifford Wolf | Added "extract -map %<design_name>" |
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2014-02-20 |
Clifford Wolf | Added "design -push" and "design -pop" |
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2014-02-20 |
Clifford Wolf | Progress in presentation |
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2014-02-20 |
Clifford Wolf | Added connwrappers command |
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2014-02-20 |
Clifford Wolf | Cleanups in handling of read_verilog -defer and -icells |
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2014-02-20 |
Clifford Wolf | Progress in presentation |
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2014-02-19 |
Clifford Wolf | Added vcd2txt.pl and txt2tikztiming.py (tests/tools... |
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2014-02-18 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-02-18 |
Clifford Wolf | Progress in presentation |
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2014-02-18 |
Clifford Wolf | Added techmap support for _TECHMAP_CONNMAP_*_ |
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2014-02-18 |
Clifford Wolf | Added "sat -dump_cnf" |
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2014-02-18 |
Clifford Wolf | Coding style corrections in SatHelper::dump_model_to_vcd() |
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2014-02-18 |
Clifford Wolf | Improved non-verbose ezSAT::printDIMACS() format |
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2014-02-18 |
Clifford Wolf | Added "sat -initsteps" |
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