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yosys.git
2019-07-09
Clifford Wolf
Merge pull request #1163 from whitequark/more-case...
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2019-07-09
Clifford Wolf
Merge pull request #1162 from whitequark/rtlil-case...
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2019-07-09
Clifford Wolf
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
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2019-07-09
Eddie Hung
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc
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2019-07-09
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-07-09
Eddie Hung
Clarify script -scriptwire doc
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2019-07-09
Eddie Hung
Add synth -keepdc to CHANGELOG
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2019-07-09
Eddie Hung
Clarify 'wreduce -keepdc' doc
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2019-07-09
Eddie Hung
Add synth -keepdc option
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2019-07-08
Eddie Hung
Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2
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2019-07-08
David Shah
Merge pull request #1160 from ZirconiumX/cyclone_v
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2019-07-08
Eddie Hung
Update muxcover doc as per @ZirconiumX
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2019-07-08
Eddie Hung
atoi -> stoi
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2019-07-08
Eddie Hung
Add muxcover -mux2=cost option
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2019-07-08
whitequark
verilog_backend: dump attributes on SwitchRule.
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2019-07-08
whitequark
proc_mux: consider \src attribute on CaseRule.
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2019-07-08
whitequark
verilog_backend: dump attributes on CaseRule, as comments.
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2019-07-08
whitequark
genrtlil: emit \src attribute on CaseRule.
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2019-07-08
whitequark
Allow attributes on individual switch cases in RTLIL.
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2019-07-07
Dan Ravensloft
synth_intel: Warn about untested Quartus backend
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2019-07-05
Clifford Wolf
Merge pull request #1159 from btut/fix/1090_segfault_ce...
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2019-07-04
Benedikt Tutzer
Throw runtime exception when trying to convert a c...
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2019-07-03
Eddie Hung
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_un...
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2019-07-03
Clifford Wolf
Merge pull request #1147 from YosysHQ/clifford/fix1144
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2019-07-03
Clifford Wolf
Fix tests/various/specify.v
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2019-07-03
Clifford Wolf
Some cleanups in "ignore specify parser"
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2019-07-03
Clifford Wolf
Merge pull request #1154 from whitequark/manual-sync...
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2019-07-03
Eddie Hung
write_xaiger to treat unknown cell connections as keep-s
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2019-07-03
Eddie Hung
Add test
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2019-07-02
Eddie Hung
Merge pull request #1150 from YosysHQ/eddie/script_from...
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2019-07-02
whitequark
manual: explain the purpose of `sync always`.
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2019-07-02
Eddie Hung
Merge branch 'eddie/script_from_wire' into eddie/xc7srl...
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2019-07-02
David Shah
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
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2019-07-02
Eddie Hung
Update test for Pass::call_on_module()
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2019-07-02
Eddie Hung
Use Pass::call_on_module() as per @cliffordwolf comments
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2019-07-02
Eddie Hung
Update test too
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2019-07-02
Eddie Hung
script -select -> script -scriptwire
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2019-07-02
David Shah
memory_dff: Fix checking of feedback mux input when...
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2019-07-02
Clifford Wolf
Fix read_verilog assert/assume/etc on default case...
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2019-07-01
Eddie Hung
Space
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2019-07-01
Eddie Hung
Move CHANGELOG entry from yosys-0.8 to 0.9
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2019-07-01
Eddie Hung
Merge branch 'master' into eddie/script_from_wire
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2019-07-01
Eddie Hung
Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG
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2019-07-01
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-06-30
Eddie Hung
Comment out invalid syntax
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2019-06-30
Eddie Hung
Cleanup SRL inference/make more consistent
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2019-06-30
Eddie Hung
install *_nowide.lut files
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2019-06-28
Eddie Hung
Merge pull request #1149 from gsomlo/gls-1098-abcext...
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2019-06-28
Eddie Hung
Merge branch 'master' into eddie/script_from_wire
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2019-06-28
Eddie Hung
autotest.sh to define _AUTOTB when test_autotb
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2019-06-28
Eddie Hung
Try command in another module
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2019-06-28
Eddie Hung
Add to CHANGELOG
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2019-06-28
Eddie Hung
Support ability for "script -select" to take commands...
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2019-06-28
Eddie Hung
Add test
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2019-06-28
Eddie Hung
Replace log_assert() with meaningful log_error()
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2019-06-28
Eddie Hung
Remove peepopt call in synth_xilinx since already in...
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2019-06-28
Gabriel L....
Make abc9 pass aware of optional ABCEXTERNAL override
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2019-06-28
Eddie Hung
Add missing CHANGELOG entries
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2019-06-28
Eddie Hung
Fix spacing
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2019-06-28
Eddie Hung
Merge pull request #1098 from YosysHQ/xaig
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2019-06-28
Eddie Hung
Add test from #1144, and try reading without '-specify...
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2019-06-28
Eddie Hung
Add generic __builtin_bswap32 function
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2019-06-28
Eddie Hung
Also fix write_aiger for UB
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2019-06-28
Eddie Hung
Fix more potential for undefined behaviour due to conta...
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2019-06-28
Eddie Hung
Update synth_ice40 -device doc to be relevant for ...
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2019-06-28
Eddie Hung
Disable boxing of ECP5 dist RAM due to regression
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2019-06-28
Eddie Hung
Add write address to abc_scc_break of ECP5 dist RAM
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2019-06-28
Eddie Hung
Fix DO4 typo
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2019-06-28
Clifford Wolf
Merge pull request #1146 from gsomlo/gls-test-abc-ext
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2019-06-28
Clifford Wolf
Improve specify dummy parser, fixes #1144
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2019-06-28
Clifford Wolf
Merge pull request #1046 from bogdanvuk/master
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2019-06-28
Gabriel L....
tests: use optional ABCEXTERNAL when specified
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2019-06-27
Eddie Hung
Reduce diff with upstream
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2019-06-27
Eddie Hung
Extraneous newline
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2019-06-27
Eddie Hung
Remove noise from ice40/cells_sim.v
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2019-06-27
Eddie Hung
Refactor for one "abc_carry" attribute on module
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2019-06-27
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-06-27
Eddie Hung
Do not use Module::remove() iterator version
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2019-06-27
Eddie Hung
Remove redundant doc
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2019-06-27
Eddie Hung
Remove &retime when abc9 -fast
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2019-06-27
Eddie Hung
Cleanup abc9.cc
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2019-06-27
Eddie Hung
Undo iterator based Module::remove() for cells, as...
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2019-06-27
Bogdan Vukobratovic
Add help for "-sat" option inside opt_rmdff. "opt"...
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2019-06-27
Bogdan Vukobratovic
Fix memory leak when one of multiple DFF cells is remov...
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Merge pull request #1139 from YosysHQ/dave/check-sim...
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Grr
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2019-06-27
Eddie Hung
Capitalisation
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2019-06-27
Eddie Hung
Make CHANGELOG clearer
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2019-06-27
Eddie Hung
Merge pull request #1143 from YosysHQ/clifford/fix1135
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Add warning if synth_xilinx -abc9 with family != xc7
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2019-06-27
Eddie Hung
Remove unneeded include
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2019-06-27
Eddie Hung
Merge origin/master
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2019-06-27
Eddie Hung
Add simcells.v, simlib.v, and some output
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2019-06-27
Eddie Hung
Add #1135 testcase
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2019-06-27
Eddie Hung
synth_xilinx -arch -> -family, consistent with older...
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2019-06-27
Eddie Hung
Merge pull request #1142 from YosysHQ/clifford/fix1132
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2019-06-27
Eddie Hung
Merge pull request #1138 from YosysHQ/koriakin/xc7nocar...
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