microwatt.git
2020-01-22 Anton BlanchardMerge pull request #146 from antonblanchard/vhpi-cleanup
2020-01-22 Anton BlanchardConsolidate VHPI code
2020-01-22 Anton BlanchardMerge pull request #145 from antonblanchard/sim_console-fix
2020-01-22 Anton Blanchardsim_console: Use cfmakeraw() and add option for ctrl...
2020-01-21 Anton BlanchardUpdate Makefile.synth after Paul's patches
2020-01-21 Anton BlanchardMerge pull request #134 from paulusmack/master
2020-01-21 Anton BlanchardMerge pull request #142 from antonblanchard/ghdl-synthe...
2020-01-21 Anton BlanchardMerge pull request #144 from antonblanchard/update...
2020-01-21 Anton BlanchardMerge pull request #143 from antonblanchard/use-docker
2020-01-21 Anton BlanchardAdd some information about GHDL backend issues
2020-01-21 Anton BlanchardAdd an option to use Docker
2020-01-21 Anton BlanchardInitial support for ghdl synthesis
2020-01-21 Anton BlanchardMerge pull request #140 from antonblanchard/rework...
2020-01-21 Anton BlanchardFix Makefile dependency issue with files in vhdl/*
2020-01-21 Anton BlanchardMerge pull request #141 from antonblanchard/update...
2020-01-20 Anton BlanchardImprove dependencies.py and add a --synth option
2020-01-19 Anton BlanchardMerge pull request #136 from antonblanchard/uart-rx...
2020-01-19 Anton BlanchardAdd a few FFs on the RX input to avoid metastability...
2020-01-19 Anton BlanchardMerge pull request #139 from antonblanchard/reduce-mem
2020-01-19 Anton BlanchardReduce simulated and default FPGA RAM to 384kB
2020-01-19 Anton BlanchardAdd log2ceil and use it in bram code
2020-01-19 Anton BlanchardMerge pull request #138 from antonblanchard/micropython...
2020-01-19 Anton BlanchardUpdate micropython
2020-01-19 Anton BlanchardMerge pull request #137 from antonblanchard/hello-world
2020-01-19 Anton Blanchardhello_world updates
2020-01-14 Paul Mackerrasdecode1: Mark subfic as pipelined
2020-01-14 Paul Mackerrascountzero: Add a register to help make timing
2020-01-14 Paul MackerrasPlumb loadstore1 input from execute1 not decode2
2020-01-14 Paul Mackerrasexecute: Implement bypass from output of execute1 to...
2020-01-14 Paul Mackerrasexecute: Move popcnt and prty instructions into the...
2020-01-14 Paul Mackerrasexecute: Do comparisons using the main adder
2020-01-14 Paul Mackerrasexecute1: Move EXTS* instruction back into execute1
2020-01-14 Paul Mackerrasexecute1: Remember dest GPR, RC, OE, XER for slow opera...
2020-01-14 Paul MackerrasMake divider hang off the side of execute1
2020-01-14 Paul MackerrasMake multiplier hang off the side of execute1
2020-01-11 Anton BlanchardMerge pull request #133 from antonblanchard/ghdl-synth
2020-01-11 Anton BlanchardMerge pull request #132 from antonblanchard/bin2hex...
2020-01-11 Anton BlanchardMove bin2hex.py to scripts/
2020-01-11 Anton BlanchardFix a ghdlsynth issue in fast_spr_num
2020-01-11 Anton BlanchardFix a ghdlsynth issue in icache
2020-01-11 Anton BlanchardRemoved unused core_terminated signal
2020-01-11 Anton BlanchardFix some ghdlsynth issues with fpga_bram
2020-01-11 Anton BlanchardFix ghdlsynth issue in register file
2020-01-11 Anton BlanchardRemove unused signal
2020-01-11 Anton BlanchardFix a ghdysynth inferred latch error in writeback
2020-01-11 Anton BlanchardFix a ghdysynth inferred latch error in execute
2020-01-11 Anton BlanchardMerge pull request #131 from antonblanchard/new-tests
2020-01-11 Anton BlanchardUpper 32 bits of XER should read as 0s
2020-01-11 Anton BlanchardDump CTR, LR and CR on sim termination, and update...
2020-01-10 Anton BlanchardMerge pull request #127 from tomtor/CR-PR
2020-01-10 Anton BlanchardMerge pull request #130 from antonblanchard/build-fix
2020-01-10 Anton BlanchardMerge pull request #129 from antonblanchard/update...
2020-01-10 Anton BlanchardPoint to upstream micropython
2020-01-06 Tom VijlbriefImplement CRNOR and friends
2020-01-04 Anton BlanchardMerge pull request #126 from sharkcz/docs
2020-01-03 Dan Horákdocument packaged fusesoc for Fedora users
2019-12-11 Anton Blanchardcontrol: Fix build issue with Fedora 31 version of...
2019-12-09 Anton BlanchardMerge pull request #122 from paulusmack/benh-sprs
2019-12-09 Anton BlanchardMerge pull request #123 from antonblanchard/spi-conf
2019-12-09 Anton BlanchardAdd SPI configuration to Xilinx constraint files
2019-12-07 Paul Mackerrasdecode2: Minor cleanup
2019-12-07 Benjamin Herrenschmidtsprs: Store common SPRs in register file
2019-12-07 Benjamin Herrenschmidtspr: Add translation from SPR to special GPR number
2019-12-07 Paul Mackerrasdivider: Fix overflow calculation
2019-12-07 Paul Mackerrasdecode1: Add OE=1 forms of add/sub, mul and div instruc...
2019-12-07 Paul Mackerrasexecute: Copy XER[SO] to CR for cmp[i] and cmpl[i]...
2019-12-07 Benjamin HerrenschmidtAdd basic XER support
2019-12-05 Benjamin Herrenschmidtdecode1: Mark ALU ops using carry as pipelined
2019-12-05 Benjamin Herrenschmidtcr_file: Check write_cr_enable
2019-11-18 Anton BlanchardMerge pull request #120 from antonblanchard/spr-decode...
2019-11-18 Anton BlanchardMerge pull request #119 from antonblanchard/reduce...
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-11-14 Benjamin Herrenschmidtcontrol: Reduce pipeline depth to 1
2019-11-14 Benjamin Herrenschmidtspr: Cleanup decoding of SPR numbers
2019-10-31 Benjamin Herrenschmidtwb_arbiter: Early master selection
2019-10-30 Benjamin Herrenschmidtwb_arbiter: Make arbiter size parametric
2019-10-30 Benjamin Herrenschmidtwb_arbiter: Avoid IDLE cycle when not changing master
2019-10-30 Benjamin Herrenschmidtram: Ack stores early
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface
2019-10-30 Benjamin HerrenschmidtMove log2/ispow2 to a utils package
2019-10-30 Benjamin Herrenschmidtram: Add block RAM pipelining
2019-10-30 Benjamin Herrenschmidtdecode: Reformat decode_types.vhdl
2019-10-30 Benjamin HerrenschmidtAdd option to not flatten hierarchy
2019-10-30 Benjamin Herrenschmidtwriteback: Slightly improve timing
2019-10-30 Benjamin Herrenschmidtsimple_ram: Turn on pipelining
2019-10-30 Benjamin Herrenschmidtwb_debug: Add wishbone pipelining support
2019-10-30 Benjamin Herrenschmidticache: Add wishbone pipelining support
2019-10-30 Benjamin Herrenschmidtdcache: Add wishbone pipelining support
2019-10-30 Benjamin Herrenschmidtfpga/bram: Generate stall signal
2019-10-30 Benjamin Herrenschmidtsimple_ram: Add pipelining support
2019-10-30 Benjamin Herrenschmidtintercon: Generate stall signals for non-pipelined...
2019-10-30 Benjamin Herrenschmidtwb_arbiter: Forward stall signals
2019-10-30 Benjamin Herrenschmidticache_tb: Initialize stop_mark
2019-10-30 Benjamin Herrenschmidtwishbone: Add stall signal
2019-10-30 Benjamin Herrenschmidtpp_uart: reformat
2019-10-25 Anton BlanchardMerge pull request #115 from antonblanchard/reduce...
2019-10-25 Anton BlanchardMerge pull request #113 from mikey/exec-sim-remove
2019-10-25 Anton BlanchardMerge pull request #114 from antonblanchard/dcache
2019-10-24 Michael NeulingRemove SIM generic from execute1
2019-10-23 Benjamin HerrenschmidtReduce wishbone address size to 32-bit
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