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microwatt.git
2020-01-11
Anton Blanchard
Removed unused core_terminated signal
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2020-01-11
Anton Blanchard
Fix some ghdlsynth issues with fpga_bram
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2020-01-11
Anton Blanchard
Fix ghdlsynth issue in register file
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2020-01-11
Anton Blanchard
Remove unused signal
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2020-01-11
Anton Blanchard
Fix a ghdysynth inferred latch error in writeback
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2020-01-11
Anton Blanchard
Fix a ghdysynth inferred latch error in execute
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2020-01-11
Anton Blanchard
Merge pull request #131 from antonblanchard/new-tests
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2020-01-11
Anton Blanchard
Upper 32 bits of XER should read as 0s
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2020-01-11
Anton Blanchard
Dump CTR, LR and CR on sim termination, and update...
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2020-01-10
Anton Blanchard
Merge pull request #127 from tomtor/CR-PR
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2020-01-10
Anton Blanchard
Merge pull request #130 from antonblanchard/build-fix
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2020-01-10
Anton Blanchard
Merge pull request #129 from antonblanchard/update...
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2020-01-10
Anton Blanchard
Point to upstream micropython
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2020-01-06
Tom Vijlbrief
Implement CRNOR and friends
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2020-01-04
Anton Blanchard
Merge pull request #126 from sharkcz/docs
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2020-01-03
Dan Horák
document packaged fusesoc for Fedora users
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2019-12-11
Anton Blanchard
control: Fix build issue with Fedora 31 version of...
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2019-12-09
Anton Blanchard
Merge pull request #122 from paulusmack/benh-sprs
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2019-12-09
Anton Blanchard
Merge pull request #123 from antonblanchard/spi-conf
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2019-12-09
Anton Blanchard
Add SPI configuration to Xilinx constraint files
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2019-12-07
Paul Mackerras
decode2: Minor cleanup
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2019-12-07
Benjamin Herrenschmidt
sprs: Store common SPRs in register file
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2019-12-07
Benjamin Herrenschmidt
spr: Add translation from SPR to special GPR number
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2019-12-07
Paul Mackerras
divider: Fix overflow calculation
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2019-12-07
Paul Mackerras
decode1: Add OE=1 forms of add/sub, mul and div instruc...
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2019-12-07
Paul Mackerras
execute: Copy XER[SO] to CR for cmp[i] and cmpl[i]...
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2019-12-07
Benjamin Herrenschmidt
Add basic XER support
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2019-12-05
Benjamin Herrenschmidt
decode1: Mark ALU ops using carry as pipelined
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2019-12-05
Benjamin Herrenschmidt
cr_file: Check write_cr_enable
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2019-11-18
Anton Blanchard
Merge pull request #120 from antonblanchard/spr-decode...
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2019-11-18
Anton Blanchard
Merge pull request #119 from antonblanchard/reduce...
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2019-11-15
Anton Blanchard
Merge pull request #118 from antonblanchard/bus-pipeline
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2019-11-14
Benjamin Herrenschmidt
control: Reduce pipeline depth to 1
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2019-11-14
Benjamin Herrenschmidt
spr: Cleanup decoding of SPR numbers
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2019-10-31
Benjamin Herrenschmidt
wb_arbiter: Early master selection
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2019-10-30
Benjamin Herrenschmidt
wb_arbiter: Make arbiter size parametric
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2019-10-30
Benjamin Herrenschmidt
wb_arbiter: Avoid IDLE cycle when not changing master
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2019-10-30
Benjamin Herrenschmidt
ram: Ack stores early
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2019-10-30
Benjamin Herrenschmidt
ram: Rework main RAM interface
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2019-10-30
Benjamin Herrenschmidt
Move log2/ispow2 to a utils package
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2019-10-30
Benjamin Herrenschmidt
ram: Add block RAM pipelining
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2019-10-30
Benjamin Herrenschmidt
decode: Reformat decode_types.vhdl
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2019-10-30
Benjamin Herrenschmidt
Add option to not flatten hierarchy
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2019-10-30
Benjamin Herrenschmidt
writeback: Slightly improve timing
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2019-10-30
Benjamin Herrenschmidt
simple_ram: Turn on pipelining
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2019-10-30
Benjamin Herrenschmidt
wb_debug: Add wishbone pipelining support
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2019-10-30
Benjamin Herrenschmidt
icache: Add wishbone pipelining support
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2019-10-30
Benjamin Herrenschmidt
dcache: Add wishbone pipelining support
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2019-10-30
Benjamin Herrenschmidt
fpga/bram: Generate stall signal
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2019-10-30
Benjamin Herrenschmidt
simple_ram: Add pipelining support
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2019-10-30
Benjamin Herrenschmidt
intercon: Generate stall signals for non-pipelined...
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2019-10-30
Benjamin Herrenschmidt
wb_arbiter: Forward stall signals
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2019-10-30
Benjamin Herrenschmidt
icache_tb: Initialize stop_mark
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2019-10-30
Benjamin Herrenschmidt
wishbone: Add stall signal
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2019-10-30
Benjamin Herrenschmidt
pp_uart: reformat
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2019-10-25
Anton Blanchard
Merge pull request #115 from antonblanchard/reduce...
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2019-10-25
Anton Blanchard
Merge pull request #113 from mikey/exec-sim-remove
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2019-10-25
Anton Blanchard
Merge pull request #114 from antonblanchard/dcache
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2019-10-24
Michael Neuling
Remove SIM generic from execute1
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2019-10-23
Benjamin Herrenschmidt
Reduce wishbone address size to 32-bit
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2019-10-23
Benjamin Herrenschmidt
Make it possible to change wishbone address size
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2019-10-23
Benjamin Herrenschmidt
dcache: Add testbench
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2019-10-23
Benjamin Herrenschmidt
insn: Simplistic implementation of icbi
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2019-10-23
Benjamin Herrenschmidt
insn: Implement isync instruction
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2019-10-23
Benjamin Herrenschmidt
icache & dcache: Fix store way variable
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2019-10-23
Benjamin Herrenschmidt
dcache: Cleanup (mostly cosmetic)
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2019-10-23
Benjamin Herrenschmidt
icache/dcache: Make both caches 32 lines, 2 ways
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2019-10-23
Benjamin Herrenschmidt
dcache: Introduce an extra cycle latency to make timing
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2019-10-23
Benjamin Herrenschmidt
dcache: Add a dcache
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2019-10-23
Benjamin Herrenschmidt
icache: Reduce simulation warnings
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2019-10-23
Benjamin Herrenschmidt
cache_ram: Add write-enables
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2019-10-23
Benjamin Herrenschmidt
plru: Improve sensitivity list
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2019-10-21
Anton Blanchard
Merge pull request #112 from hughhalf/patch-1
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2019-10-21
Hugh
Minor tweaks to README.md
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2019-10-19
Anton Blanchard
Merge pull request #110 from antonblanchard/misc
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2019-10-18
Benjamin Herrenschmidt
icache_tb: Improve test and include test file
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2019-10-17
Anton Blanchard
Merge pull request #109 from antonblanchard/misc
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2019-10-17
Anton Blanchard
isel takes a CR bit, not a CR field
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2019-10-16
Benjamin Herrenschmidt
common: Reformat
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2019-10-16
Benjamin Herrenschmidt
execute1: Remove mux on "write_data" and "rc" outputs
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2019-10-16
Benjamin Herrenschmidt
crhelpers: Constraint "crnum" integer
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2019-10-16
Benjamin Herrenschmidt
execute1: Reformat
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2019-10-16
Benjamin Herrenschmidt
writeback: Remove a mux leg on data_in
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2019-10-16
Anton Blanchard
Merge pull request #105 from paulusmack/writeback
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2019-10-15
Paul Mackerras
writeback: Eliminate inferred latch
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2019-10-15
Anton Blanchard
Merge pull request #106 from paulusmack/master
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2019-10-15
Paul Mackerras
wishbone_debug_master: Improve timing
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2019-10-15
Paul Mackerras
Remove execute2 stage
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2019-10-15
Anton Blanchard
Merge pull request #104 from paulusmack/master
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2019-10-15
Paul Mackerras
Do sign-extension instructions in writeback instead...
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2019-10-15
Paul Mackerras
writeback: Do data formatting and condition recording...
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2019-10-15
Anton Blanchard
Merge pull request #103 from paulusmack/divider
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2019-10-15
Paul Mackerras
Implement neg using OP_ADD
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2019-10-15
Paul Mackerras
divider: Reduce delay in detecting 32-bit overflow
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2019-10-15
Anton Blanchard
Merge pull request #102 from antonblanchard/gpr-hazard-5-c
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2019-10-15
Anton Blanchard
Add CR hazard detection
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2019-10-15
Anton Blanchard
Merge pull request #101 from antonblanchard/gpr-hazard-5-b
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2019-10-14
Paul Mackerras
divider: Add an output register
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2019-10-14
Anton Blanchard
Remove issue restrictions on a number of instructions
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2019-10-14
Anton Blanchard
Add GPR hazard detection
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