yosys.git
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec
2018-12-17 Clifford WolfMerge pull request #744 from whitequark/write_verilog_...
2018-12-16 Clifford WolfMerge pull request #745 from YosysHQ/revert-714-abc_pre...
2018-12-16 Clifford WolfRevert "Proof-of-concept: preserve naming through ABC...
2018-12-16 whitequarkwrite_verilog: handle the $shift cell.
2018-12-16 whitequarkUpdate CHANGELOG.
2018-12-16 whitequarkread_ilang: allow slicing sigspecs.
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 whitequarkselect: print selection if a -assert-* flag causes...
2018-12-16 Clifford WolfRename "fine:" label to "map:" in "synth_ice40"
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 whitequarkwrite_verilog: add a missing newline.
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes
2018-12-16 Clifford WolfMerge pull request #739 from whitequark/patch-1
2018-12-16 whitequarkAdd .editorconfig file.
2018-12-16 Clifford WolfFix equiv_opt indenting
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #734 from grahamedgecombe/fix-shuffl...
2018-12-16 Clifford WolfMerge pull request #730 from smunaut/ffssr_dont_touch
2018-12-16 Clifford WolfMerge pull request #729 from whitequark/write_verilog_i...
2018-12-16 Clifford WolfMerge pull request #725 from olofk/ram4k-init
2018-12-16 Clifford WolfMerge pull request #714 from daveshah1/abc_preserve_naming
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map...
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src
2018-12-16 Clifford WolfMerge pull request #720 from whitequark/master
2018-12-14 Sylvain Munautverilog_parser: Properly handle recursion when processi...
2018-12-12 David Shahdeminout: Consider $tribuf cells
2018-12-12 David Shahdeminout: Don't demote constant-driven inouts to inputs
2018-12-11 Graham Edgecombememory_bram: Fix initdata bit order after shuffling
2018-12-10 Clifford WolfAdd yosys-smtbmc support for btor witness
2018-12-08 Sylvain Munautice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-08 Clifford WolfAdd "yosys-smtbmc --btorwit" skeleton
2018-12-08 Clifford WolfFix btor init value handling
2018-12-07 whitequarkwrite_verilog: correctly map RTLIL `sync init`.
2018-12-07 whitequarkequiv_opt: pass -D EQUIV when techmapping.
2018-12-07 whitequarkequiv_opt: new command, for verifying optimization...
2018-12-07 David ShahMerge pull request #727 from whitequark/opt_lut
2018-12-07 whitequarkopt_lut: leave intact LUTs with cascade feeding module...
2018-12-07 whitequarkopt_lut: show original truth table for both cells.
2018-12-07 whitequarkopt_lut: add -limit option, for debugging misoptimizations.
2018-12-06 Olof KindgrenOnly use non-blocking assignments of SB_RAM40_4K for...
2018-12-06 David Shahabc: Preserve naming through ABC using 'dress' command
2018-12-06 whitequarksynth_ice40: split `map_gates` off `fine`.
2018-12-06 Clifford WolfAdd missing .gitignore
2018-12-06 Clifford WolfBugfix in opt_expr handling of a<0 and a>=0
2018-12-06 Clifford WolfVerific updates
2018-12-05 whitequarkrename: add -src, for inferring names from source locat...
2018-12-05 whitequarklut2mux: handle 1-bit INIT constant in $lut cells.
2018-12-05 whitequarkopt_lut: simplify type conversion. NFC.
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut
2018-12-05 whitequarksynth_ice40: add -noabc option, to use built-in LUT...
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to...
2018-12-05 whitequarkFix typo.
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support
2018-12-05 Clifford WolfRename opt_lut.cpp to opt_lut.cc
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut
2018-12-05 Clifford WolfMerge pull request #716 from whitequark/ice40_unlut
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such...
2018-12-05 whitequarkopt_lut: always prefer to eliminate 1-LUTs.
2018-12-05 whitequarkopt_lut: collect and display statistics.
2018-12-05 whitequarkopt_lut: refactor to use a worker. NFC.
2018-12-05 whitequarksynth_ice40: add -relut option, to run ice40_unlut...
2018-12-05 whitequarkopt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 whitequarkExtract ice40_unlut pass from ice40_opt.
2018-12-05 Serge BazanskiMerge pull request #719 from YosysHQ/q3k/flailing-aroun...
2018-12-05 Sergiusz Bazanskitravis/osx: fix, use clang instead of gcc
2018-12-04 Clifford WolfFix typo
2018-12-04 Clifford WolfMerge pull request #702 from smunaut/min_ce_use
2018-12-04 Diego HChanges in GoWin synth commands and ALU primitive support
2018-12-02 Miodrag MilanovicLeave only real black box cells
2018-12-01 Miodrag MilanovicInitial support for Anlogic FPGA
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-29 Clifford WolfImprove ConstEval error handling for non-eval cell...
2018-11-27 Sylvain Munautice40: Add option to only use CE if it'd be use by...
2018-11-27 Sylvain Munautdff2dffe: Add option for unmap to only remove DFFE...
2018-11-24 Sylvain MunautMake return value of $clog2 signed
2018-11-20 Clifford WolfAdd iteration limit to "opt_muxtree"
2018-11-19 Daniël W. CromptonUsing awk rather than gawk
2018-11-13 Clifford WolfUpdate ABC to git rev 2ddc57d
2018-11-12 Clifford WolfAdd "write_aiger -I -O -B"
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-11 Clifford WolfUpdate ABC to git rev 68da3cf
2018-11-10 Eddie HungAdd support for Xilinx PS7 block
2018-11-09 Clifford WolfSet Verific flag vhdl_support_variable_slice=1
2018-11-09 David Shahecp5: Add 'fake' DCU parameters
2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells
2018-11-09 Clifford WolfMerge pull request #696 from arjenroodselaar/verific_darwin
2018-11-08 Clifford WolfFix "make ystests" to use correct Yosys binary
2018-11-08 Arjen RoodselaarUse appropriate static libraries when building with...
2018-11-07 Clifford WolfMerge pull request #693 from YosysHQ/rlimit
2018-11-07 David Shahecp5: Adding some blackbox cells
2018-11-07 Clifford WolfLimit stack size to 16 MB on Darwin
2018-11-06 Clifford WolfMerge pull request #694 from trcwm/dffmap_expr_fix
2018-11-06 Niels MoseleyDFFLIBMAP: changed 'missing pin' error into a warning...
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