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yosys.git
2018-12-17
Clifford Wolf
Merge pull request #742 from whitequark/changelog
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2018-12-17
Clifford Wolf
Merge pull request #741 from whitequark/ilang_slice_sigspec
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2018-12-17
Clifford Wolf
Merge pull request #744 from whitequark/write_verilog_...
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2018-12-16
Clifford Wolf
Merge pull request #745 from YosysHQ/revert-714-abc_pre...
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2018-12-16
Clifford Wolf
Revert "Proof-of-concept: preserve naming through ABC...
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2018-12-16
whitequark
write_verilog: handle the $shift cell.
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2018-12-16
whitequark
Update CHANGELOG.
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2018-12-16
whitequark
read_ilang: allow slicing sigspecs.
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2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
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2018-12-16
whitequark
select: print selection if a -assert-* flag causes...
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2018-12-16
Clifford Wolf
Rename "fine:" label to "map:" in "synth_ice40"
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2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
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2018-12-16
whitequark
write_verilog: add a missing newline.
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2018-12-16
Clifford Wolf
Merge pull request #738 from smunaut/issue_737
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2018-12-16
Clifford Wolf
Merge pull request #735 from daveshah1/trifixes
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2018-12-16
Clifford Wolf
Merge pull request #739 from whitequark/patch-1
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2018-12-16
whitequark
Add .editorconfig file.
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2018-12-16
Clifford Wolf
Fix equiv_opt indenting
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2018-12-16
Clifford Wolf
Merge pull request #724 from whitequark/equiv_opt
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2018-12-16
Clifford Wolf
Merge pull request #734 from grahamedgecombe/fix-shuffl...
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2018-12-16
Clifford Wolf
Merge pull request #730 from smunaut/ffssr_dont_touch
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2018-12-16
Clifford Wolf
Merge pull request #729 from whitequark/write_verilog_i...
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2018-12-16
Clifford Wolf
Merge pull request #725 from olofk/ram4k-init
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2018-12-16
Clifford Wolf
Merge pull request #714 from daveshah1/abc_preserve_naming
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2018-12-16
Clifford Wolf
Merge pull request #723 from whitequark/synth_ice40_map...
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2018-12-16
Clifford Wolf
Merge pull request #722 from whitequark/rename_src
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2018-12-16
Clifford Wolf
Merge pull request #720 from whitequark/master
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2018-12-14
Sylvain Munaut
verilog_parser: Properly handle recursion when processi...
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2018-12-12
David Shah
deminout: Consider $tribuf cells
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2018-12-12
David Shah
deminout: Don't demote constant-driven inouts to inputs
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2018-12-11
Graham Edgecombe
memory_bram: Fix initdata bit order after shuffling
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2018-12-10
Clifford Wolf
Add yosys-smtbmc support for btor witness
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2018-12-08
Sylvain Munaut
ice40: Honor the "dont_touch" attribute in FFSSR pass
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2018-12-08
Clifford Wolf
Add "yosys-smtbmc --btorwit" skeleton
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2018-12-08
Clifford Wolf
Fix btor init value handling
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2018-12-07
whitequark
write_verilog: correctly map RTLIL `sync init`.
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2018-12-07
whitequark
equiv_opt: pass -D EQUIV when techmapping.
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2018-12-07
whitequark
equiv_opt: new command, for verifying optimization...
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2018-12-07
David Shah
Merge pull request #727 from whitequark/opt_lut
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2018-12-07
whitequark
opt_lut: leave intact LUTs with cascade feeding module...
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2018-12-07
whitequark
opt_lut: show original truth table for both cells.
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2018-12-07
whitequark
opt_lut: add -limit option, for debugging misoptimizations.
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2018-12-06
Olof Kindgren
Only use non-blocking assignments of SB_RAM40_4K for...
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2018-12-06
David Shah
abc: Preserve naming through ABC using 'dress' command
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2018-12-06
whitequark
synth_ice40: split `map_gates` off `fine`.
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2018-12-06
Clifford Wolf
Add missing .gitignore
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2018-12-06
Clifford Wolf
Bugfix in opt_expr handling of a<0 and a>=0
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2018-12-06
Clifford Wolf
Verific updates
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2018-12-05
whitequark
rename: add -src, for inferring names from source locat...
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2018-12-05
whitequark
lut2mux: handle 1-bit INIT constant in $lut cells.
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2018-12-05
whitequark
opt_lut: simplify type conversion. NFC.
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2018-12-05
Clifford Wolf
Merge pull request #709 from smunaut/issue_708
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2018-12-05
Clifford Wolf
Merge pull request #718 from whitequark/gate2lut
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2018-12-05
whitequark
synth_ice40: add -noabc option, to use built-in LUT...
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2018-12-05
whitequark
gate2lut: new techlib, for converting Yosys gates to...
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2018-12-05
whitequark
Fix typo.
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2018-12-05
Clifford Wolf
Merge pull request #713 from Diego-HR/master
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2018-12-05
Clifford Wolf
Merge pull request #712 from mmicko/anlogic-support
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2018-12-05
Clifford Wolf
Rename opt_lut.cpp to opt_lut.cc
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2018-12-05
Clifford Wolf
Merge pull request #717 from whitequark/opt_lut
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2018-12-05
Clifford Wolf
Merge pull request #716 from whitequark/ice40_unlut
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2018-12-05
whitequark
opt_lut: add -dlogic, to avoid disturbing logic such...
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2018-12-05
whitequark
opt_lut: always prefer to eliminate 1-LUTs.
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2018-12-05
whitequark
opt_lut: collect and display statistics.
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2018-12-05
whitequark
opt_lut: refactor to use a worker. NFC.
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2018-12-05
whitequark
synth_ice40: add -relut option, to run ice40_unlut...
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2018-12-05
whitequark
opt_lut: new pass, to combine LUTs for tighter packing.
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2018-12-05
whitequark
Extract ice40_unlut pass from ice40_opt.
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2018-12-05
Serge Bazanski
Merge pull request #719 from YosysHQ/q3k/flailing-aroun...
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2018-12-05
Sergiusz Bazanski
travis/osx: fix, use clang instead of gcc
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2018-12-04
Clifford Wolf
Fix typo
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2018-12-04
Clifford Wolf
Merge pull request #702 from smunaut/min_ce_use
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2018-12-04
Diego H
Changes in GoWin synth commands and ALU primitive support
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2018-12-02
Miodrag Milanovic
Leave only real black box cells
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2018-12-01
Miodrag Milanovic
Initial support for Anlogic FPGA
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2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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2018-11-29
Clifford Wolf
Improve ConstEval error handling for non-eval cell...
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2018-11-27
Sylvain Munaut
ice40: Add option to only use CE if it'd be use by...
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2018-11-27
Sylvain Munaut
dff2dffe: Add option for unmap to only remove DFFE...
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2018-11-24
Sylvain Munaut
Make return value of $clog2 signed
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2018-11-20
Clifford Wolf
Add iteration limit to "opt_muxtree"
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2018-11-19
Daniël W. Crompton
Using awk rather than gawk
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2018-11-13
Clifford Wolf
Update ABC to git rev 2ddc57d
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2018-11-12
Clifford Wolf
Add "write_aiger -I -O -B"
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2018-11-12
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-11-12
Clifford Wolf
Merge pull request #697 from eddiehung/xilinx_ps7
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-11
Clifford Wolf
Update ABC to git rev 68da3cf
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2018-11-10
Eddie Hung
Add support for Xilinx PS7 block
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2018-11-09
Clifford Wolf
Set Verific flag vhdl_support_variable_slice=1
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2018-11-09
David Shah
ecp5: Add 'fake' DCU parameters
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2018-11-09
David Shah
ecp5: Add blackboxes for ancillary DCU cells
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2018-11-09
Clifford Wolf
Merge pull request #696 from arjenroodselaar/verific_darwin
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2018-11-08
Clifford Wolf
Fix "make ystests" to use correct Yosys binary
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2018-11-08
Arjen Roodselaar
Use appropriate static libraries when building with...
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2018-11-07
Clifford Wolf
Merge pull request #693 from YosysHQ/rlimit
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2018-11-07
David Shah
ecp5: Adding some blackbox cells
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2018-11-07
Clifford Wolf
Limit stack size to 16 MB on Darwin
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2018-11-06
Clifford Wolf
Merge pull request #694 from trcwm/dffmap_expr_fix
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2018-11-06
Niels Moseley
DFFLIBMAP: changed 'missing pin' error into a warning...
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