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yosys.git
2019-08-23
Eddie Hung
Revert to upstream
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2019-08-23
Eddie Hung
Fix spacing
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2019-08-23
Eddie Hung
Remove unused model
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2019-08-23
Eddie Hung
Put attributes above port
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-23
Eddie Hung
Forgot one
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2019-08-23
Eddie Hung
Put abc_* attributes above port
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2019-08-23
Eddie Hung
Merge pull request #1326 from mmicko/doc-update
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2019-08-23
Miodrag Milanovic
Make macOS depenency clear
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2019-08-22
Eddie Hung
Do not propagate mem2reg attribute through to result
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2019-08-22
Eddie Hung
Spelling
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2019-08-22
Eddie Hung
Merge pull request #1322 from mmicko/pyosys_osx
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2019-08-22
Miodrag Milanovic
do not require boost if pyosys is not used
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2019-08-22
Eddie Hung
Merge pull request #1319 from TeaEngineering/shuckc...
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2019-08-22
Eddie Hung
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
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2019-08-22
Clifford Wolf
Bump year in copyright notice
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2019-08-22
Clifford Wolf
Fix missing newline at end of file
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2019-08-22
Clifford Wolf
Merge pull request #1289 from mmicko/anlogic_fixes
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2019-08-22
Clifford Wolf
Fix missing newline at end of file
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2019-08-22
Clifford Wolf
Merge pull request #1281 from mmicko/efinix
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2019-08-22
Eddie Hung
Copy-paste typo
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2019-08-22
Chris Shucksmith
require tcl-tk in Brewfile
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2019-08-22
Eddie Hung
Respect opt_expr -keepdc as per @cliffordwolf
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2019-08-22
Eddie Hung
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
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2019-08-22
Eddie Hung
Add cover()
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2019-08-22
Eddie Hung
Canonical form
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2019-08-22
Clifford Wolf
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg
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2019-08-22
Eddie Hung
Add test
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2019-08-22
Eddie Hung
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-21
whitequark
Merge pull request #1315 from mmicko/fix_dependencies
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2019-08-21
Eddie Hung
mem2reg to preserve user attributes and src
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2019-08-21
Eddie Hung
Use semicolon
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2019-08-21
Eddie Hung
techmap before read
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2019-08-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-21
Eddie Hung
Output "h" extension only if boxes
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2019-08-21
Eddie Hung
Revert "Fix omode which inserts an output if none exist...
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2019-08-21
Eddie Hung
Add abc_arrival to SRL*
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2019-08-21
Miodrag Milanovic
Fix test_pmgen deps
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2019-08-21
Clifford Wolf
Merge pull request #1314 from YosysHQ/eddie/fix_techmap
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2019-08-21
Eddie Hung
Fix omode which inserts an output if none exists (other...
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2019-08-21
Eddie Hung
Revert "Only xaig if GetSize(output_bits) > 0"
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2019-08-21
Eddie Hung
Only xaig if GetSize(output_bits) > 0
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2019-08-21
Eddie Hung
Missing newline
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2019-08-21
Eddie Hung
Fix copy-paste typo
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2019-08-21
Eddie Hung
Oops
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2019-08-21
Eddie Hung
Merge branch 'eddie/fix_techmap' into xaig_arrival
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2019-08-21
Eddie Hung
Grammar
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2019-08-21
Eddie Hung
Add test
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2019-08-21
Eddie Hung
techmap -max_iter to apply to each module individually
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2019-08-21
Eddie Hung
techmap -max_iter to apply to each module individually
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2019-08-21
Eddie Hung
xilinx to use abc_map.v with -max_iter 1
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2019-08-21
Eddie Hung
ecp5: remove DPR16X4 from abc_unmap.v
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2019-08-21
Eddie Hung
ecp5 to use -max_iter 1
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2019-08-21
Eddie Hung
ecp5 to use abc_map.v and _unmap.v
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2019-08-21
Eddie Hung
Add (* abc_arrival=<int> *) doc
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2019-08-21
Eddie Hung
Add reference to FD* timing
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2019-08-21
Eddie Hung
Remove sequential extension
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2019-08-21
Eddie Hung
Remove SRL* delays from cells_sim.v
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2019-08-21
Eddie Hung
retime_mode -> dff_mode
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2019-08-21
Eddie Hung
LUTMUX -> LUTMUX6
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2019-08-21
Eddie Hung
Cleanup techmap in map_luts
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2019-08-21
Eddie Hung
Move `techmap abc_map.v` into map_luts
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2019-08-21
Eddie Hung
Remove delays from abc_map.v
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2019-08-21
Eddie Hung
Typo
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2019-08-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-20
Eddie Hung
Do not sigmap!
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2019-08-20
Eddie Hung
Deprecate `abc_scc_break` attribute
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2019-08-20
Eddie Hung
Wrap SRL{16,32} too
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2019-08-20
Eddie Hung
Wrap LUTRAMs in order to capture comb/seq behaviour
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2019-08-20
Eddie Hung
Minor refactor
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2019-08-20
Eddie Hung
Add LUTRAM delays
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2019-08-20
Eddie Hung
Fix use of {CLK,EN}_POLARITY, also add a FIXME
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2019-08-20
Eddie Hung
Remove mapping rules
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2019-08-20
Eddie Hung
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
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2019-08-20
Eddie Hung
Remove -icells
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2019-08-20
Eddie Hung
Use abc_{map,unmap,model}.v
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2019-08-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-20
Eddie Hung
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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2019-08-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-20
Clifford Wolf
Merge pull request #1298 from YosysHQ/clifford/pmgen
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2019-08-20
Clifford Wolf
Merge branch 'master' into clifford/pmgen
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2019-08-20
Clifford Wolf
Add test case for real parameters
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2019-08-20
Clifford Wolf
Merge pull request #1308 from jakobwenzel/real_params
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2019-08-20
whitequark
Merge pull request #1309 from whitequark/proc_clean...
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2019-08-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-19
Eddie Hung
Add arrival times for SRL outputs
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2019-08-19
Eddie Hung
Output i/o/h extensions even if no boxes or flops
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2019-08-19
Eddie Hung
Add BRAM arrival times
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2019-08-19
Eddie Hung
Remove debug
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2019-08-19
Eddie Hung
Add reference to source of Tclktoq timing
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2019-08-19
Eddie Hung
Add (* abc_arrival *) attribute
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2019-08-19
Eddie Hung
Add 'abc_arrival' attribute for flop outputs
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2019-08-19
Eddie Hung
Update box timings
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2019-08-19
Eddie Hung
Move from cell attr to module attr
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2019-08-19
Eddie Hung
Fix typo
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2019-08-19
Eddie Hung
Fix typo
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2019-08-19
Eddie Hung
ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
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2019-08-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-19
Eddie Hung
Clarify with 'only'
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