nmigen.git
2019-07-10 William D.... build.dsl: Add optional name_suffix to Resource.family.
2019-07-10 whitequarkback.pysim: avoid malformed VCD files when a decoder...
2019-07-10 whitequarkhdl.ir: make UnusedElaboratable a real warning.
2019-07-09 whitequarkback.rtlil: add decodings to cases when switching on...
2019-07-09 whitequarkback.verilog: run proc_prune for much cleaner output.
2019-07-09 whitequarkhdl.{ast,dsl},back.rtlil: track source locations for...
2019-07-09 Jacob Lifshaytracer: add PyPy support to get_var_name().
2019-07-09 whitequarkbuild.dsl: add Resource.family abstraction.
2019-07-08 whitequarkbuild.{dsl,res}: allow platform-dependent attributes...
2019-07-08 whitequarkhdl.rec: respect modifications to signals in Record...
2019-07-08 whitequarkback.rtlil: don't name-prefix signals connected to...
2019-07-08 whitequarkbuild.{dsl,res}: allow removing attributes from subsignals.
2019-07-08 whitequarkbuild.dsl: allow assertions on subsignal widths.
2019-07-08 whitequarkhdl.{ast,cd,dsl,xfrm}: reject inappropriately used...
2019-07-08 whitequarktest: fix Travis.
2019-07-08 whitequarktest: generate examples to verilog as part of unit...
2019-07-08 whitequarkexamples/basic/ctr_ce: fix outdated syntax.
2019-07-08 whitequarkcompat.genlib.fsm: fix after commit dac62754.
2019-07-08 whitequarkhdl.xfrm: don't overwrite source locations on ClockDoma...
2019-07-08 whitequarkhdl.{dsl,mem,xfrm}: inject appropriate source locations.
2019-07-08 whitequarkback.rtlil: ignore empty source locations.
2019-07-08 whitequarkhdl.ast: use keyword-only arguments as appropriate.
2019-07-08 whitequarkback.rtlil: attach source locations to switches, not...
2019-07-08 whitequarkback.rtlil: use a more principled approach to attribute...
2019-07-07 Alain Péteutvendor.xilinx_7series: generate also binary bitfile.
2019-07-07 William D.... vendor.xilinx_spartan_3_6: Add Spartan3A family support.
2019-07-07 whitequarkvendor.lattice_ecp5: don't leave LUT inputs disconnected.
2019-07-07 whitequarkhdl.dsl: further clarify error message for incorrect...
2019-07-07 whitequarkhdl.dsl: clarify error message for incorrect nesting.
2019-07-07 whitequarkhdl.dsl: gracefully handle FSM with no states.
2019-07-07 whitequarkbuild.plat: source a script with toolchain environment.
2019-07-07 whitequarkbuild.run: only use os.path on the target OS.
2019-07-07 whitequarkbuild.run: make BuildProducts abstract, add LocalBuildP...
2019-07-06 whitequarkbuild.plat, vendor.*: don't join strings passed as...
2019-07-06 whitequarkbuild.run: make sure BuildProducts._root is not easily...
2019-07-04 Staf Verhaegenvendor.xilinx_{7series,spartan6}: Support extra VHDL...
2019-07-03 whitequarkhdl.dsl: fix src_loc_at for FSM state signal.
2019-07-03 whitequarkback.rtlil: emit \src attributes for processes via...
2019-07-03 whitequarkhdl.ast: fix src_loc_at for Mux().
2019-07-03 whitequarkbuild.res: detect physical conflicts earlier.
2019-07-03 whitequarkhdl.rec: thread src_loc_at to all inner Signals and...
2019-07-03 whitequarkvendor: give names to IO buffer instances.
2019-07-03 whitequarkhdl.rec: accept Record(src_loc_at=...).
2019-07-03 whitequarkcompat.fhdl.specials: mark CompatMemory as Elaboratable.
2019-07-03 whitequarkcompat.fhdl.specials: use "sync" as default domain...
2019-07-03 whitequarkcompat.fhdl.specials: fix Memory.get_port() after 94e8f479.
2019-07-03 whitequarkcompat.fhdl.structure: fix If/Elif/Else after 32446831.
2019-07-03 Sebastien Bourdeauducqlattice_ecp5: fix get_input
2019-07-02 whitequarkhdl.ast: recognize a Enum used as decoder and format...
2019-07-02 whitequarkhdl.mem: fix naming of registers inside unnamed memories.
2019-07-02 Alain Péteutbuild.plat: add iter_extra_files method.
2019-07-02 whitequarkback.rtlil: emit \sig$next wires instead of \$next...
2019-07-02 whitequarkback.rtlil: do not emit $next wires for comb signals.
2019-07-02 whitequarkhdl.rec: implement slicing by component names.
2019-07-02 whitequarkhdl.rec: implement Record.like.
2019-07-02 Alain Péteutvendor.xilinx_7series: read extra .xdc files.
2019-07-01 whitequarkhdl.mem: use read_port(domain="comb") for asynchronous...
2019-07-01 whitequarkback.rtlil: fix Array regression in 32446831.
2019-06-28 whitequarkback.pysim: create unique ResetSynchronizer internal...
2019-06-28 whitequarkback.pysim: override ResetSynchronizer implementation.
2019-06-28 whitequarklib.cdc: avoid interior clock domains in ResetSynchronizer.
2019-06-28 whitequarklib.cdc: eliminate no_retiming attributes.
2019-06-28 whitequarkvendor.lattice_ice40: fix instance of negedge FF due...
2019-06-28 Alain Péteutbuild.plat: fix dedent overrides.
2019-06-28 whitequarkREADME: tone down the instability warning to reflect...
2019-06-28 whitequarkhdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case...
2019-06-28 whitequarkhdl.ir, back.rtlil: allow specifying attributes on...
2019-06-27 whitequarkexamples: add concise UART example.
2019-06-26 whitequarkback.pysim: fix scope screwup.
2019-06-25 whitequarkcompat.fhdl.structure: fix typo.
2019-06-25 whitequarkcompat.fhdl.structure: simplify handling of default...
2019-06-25 whitequarkhdl.{ast,dst}: directly represent RTLIL default case.
2019-06-25 whitequarkvendor.xilinx_{spartan6,7series}: speedgrade→speed.
2019-06-25 whitequarkvendor.lattice_ecp5: implement.
2019-06-24 Sebastien BourdeauducqREADME: update nMigen libs paragraph
2019-06-24 Sebastien BourdeauducqREADME: add clarification about HLS
2019-06-19 whitequarkvendor.lattice_ice40: use different --package for 4k...
2019-06-17 Jean-François... vendor.xilinx_7series: fix IOB packing.
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explic...
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: cleanup. NFC.
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: connect FCDE and...
2019-06-16 Alain Péteutbuild.plat: dedent overrides.
2019-06-14 whitequarkvendor.lattice_ice40: never place an inverter on global...
2019-06-13 Jean-François... vendor.xilinx_7series: implement inverters.
2019-06-13 Jean-François... vendor.xilinx_spartan6: implement DDR I/O buffers and...
2019-06-13 whitequarkcompat.fhdl.structure: fix Case().makedefault().
2019-06-13 whitequarkcompat.fhdl.structure: always order default case as...
2019-06-13 whitequarkhdl.ast: tighten assertion in Switch().
2019-06-12 whitequarkSimplify code by using Signal.like(name_suffix=".....
2019-06-12 whitequarkhdl.ast: add name_suffix=".." option to Signal.like().
2019-06-12 Jean-François... vendor.xilinx_7series: implement DDR I/O buffers.
2019-06-12 whitequarkvendor.lattice_ice40: fix typo.
2019-06-12 whitequarkbuild.{dsl,res,plat}: add PinsN and DiffPairsN.
2019-06-11 whitequarkhdl.ast: implement values with custom lowering.
2019-06-11 whitequarkback.pysim: check for a clock being added twice.
2019-06-11 whitequarkback.rtlil: mask memory init values.
2019-06-11 whitequarkhdl.mem: coerce memory init values to integers.
2019-06-09 Simon Kirkbylib.cdc: fix typo.
2019-06-07 Jean-François... vendor.xilinx_spartan6: implement.
2019-06-07 Jean-François... vendor.xilinx_7series: fix typos.
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