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nmigen.git
2018-12-14 whitequarkback.pysim: use bare ints for signal values (-5% runtime). commit | commitdiff | tree
2018-12-14 whitequarksetup: add missing import. commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: collect handlers before running (-5% runtime). commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: allow multiple registered handlers per... commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: fix handling of process termination. commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: new simulator backend (WIP). commit | commitdiff | tree
2018-12-13 whitequarkfhdl.cd: rename ClockDomain signals together with domain. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: move Fragment prepare logic from back.rtlil. commit | commitdiff | tree
2018-12-13 whitequarkback.verilog: remove debug code. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: record port direction explicitly. commit | commitdiff | tree
2018-12-13 whitequarkcompat.genlib.fsm: import/wrap Migen code. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: a subfragment's input that we don't drive... commit | commitdiff | tree
2018-12-13 whitequarkfhdl, back: trace and emit source locations of values. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: never give subfragment cells names starting... commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: don't crash propagataing ports in empty fragments. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: remove iter_domains(). commit | commitdiff | tree
2018-12-13 whitequarkfhdl: cd_name→domain. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.cd: add tests. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.xfrm: implement DomainRenamer. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.xfrm: add test for ControlInserter with subfragments. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.xfrm: add tests for ResetInserter, CEInserter. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: add tests for port propagation. commit | commitdiff | tree
2018-12-13 whitequarkSet up Travis CI. commit | commitdiff | tree
2018-12-13 whitequarkAdd LICENSE. commit | commitdiff | tree
2018-12-13 whitequarksetup: check Python version. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: add tests for lowering. 99% branch coverage. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.cd: rename ClockDomain.{reset→rst}. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: add tests for submodules. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level... commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ast: fix Switch._?hs_signals() for switch without... commit | commitdiff | tree
2018-12-13 whitequarkback.verilog: detect undriven public wires using Yosys. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: fix swapped operands in sync assign. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: explain logic for CD reset insertion. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: explicitly set the top module. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: explain how port enumeration works. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: explain how RTLIL conversion works. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: make sure clocks and resets of used CDs appear... commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: give clocks and resets nicer names. commit | commitdiff | tree
2018-12-13 whitequarkcompat.fhdl.module: implement finalization. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: match shape of $mux ports A/B/Y. commit | commitdiff | tree
2018-12-13 whitequarktracer: add support for Python 3.7. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ast: bits_sign→shape. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ast: add tests for most logic. commit | commitdiff | tree
2018-12-13 whitequarkMeasure test coverage. commit | commitdiff | tree
2018-12-12 whitequarkcompat.fhdl.{module,structure}: import/wrap Migen code... commit | commitdiff | tree
2018-12-12 whitequarkcompat.fhdl.bitcontainer: import/wrap Migen code. commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ast.Signal: implement .like(). commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ir: fix port threading code. commit | commitdiff | tree
2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix. commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ast.Signal: fix typo. commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ast.Signal: implement attrs field. commit | commitdiff | tree
2018-12-12 whitequarkgenlib.cdc.MultiReg: self.regs should be a private... commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ast.Signal: implement width derivation from min... commit | commitdiff | tree
2018-12-12 whitequarkgenlib.cdc.MultiReg: pull in from Migen. commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ast.Signal: implement reset_less signals. commit | commitdiff | tree
2018-12-12 whitequarkfhdl.ast.Signal: assign an internal name if tracer... commit | commitdiff | tree
2018-12-12 whitequarkfhdl.dsl: allow f.sync["dom"] as a synonym of f.sync... commit | commitdiff | tree
2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInse... commit | commitdiff | tree
2018-12-12 whitequarkInitial commit. commit | commitdiff | tree