yosys.git
2019-03-19 Eddie HungAdd author name
2019-02-19 Eddie HungAdd aiger tests to make tests
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-19 Eddie HungFix for using POSIX basename
2019-02-18 Eddie HungMissing OSX headers?
2019-02-18 Eddie HungRevert "Missing headers for Xcode?"
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement...
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells"
2019-02-17 Eddie Hungread_aiger to ignore line after ands for ascii, not...
2019-02-17 Eddie HungOne more merge conflict
2019-02-17 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-15 Jim LawsonRemoved unused variables, functions.
2019-02-15 Jim LawsonAppend (instead of over-writing) EXTRA_FLAGS
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-13 Clifford WolfFix sign handling of real constants
2019-02-12 Eddie HungMissing headers for Xcode?
2019-02-12 Eddie HungMerge branch 'read_aiger' of github.com:eddiehung/yosys...
2019-02-12 Eddie HungUse module->add{Not,And}Gate() functions
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a...
2019-02-12 Clifford WolfMerge pull request #806 from daveshah1/fsm_opt_no_reset
2019-02-11 Eddie HungDo not break for constraints
2019-02-11 Eddie HungNo increment line_count for binary ANDs
2019-02-11 Eddie HungDo not ignore newline after AND in binary AIG
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-08 Eddie HungaddDff -> addDffGate as per @daveshah1
2019-02-08 Eddie HungFix tabulation
2019-02-08 Eddie Hung-module_name arg to go before -clk_name
2019-02-08 Eddie HungSupport and differentiate between ASCII and binary...
2019-02-08 Eddie HungAdd missing "[options]" to read_blif help
2019-02-08 Eddie HungAllow module name to be determined by argument too
2019-02-08 Eddie HungRefactor into AigerReader class
2019-02-08 Eddie HungParse binary AIG files
2019-02-08 Eddie HungAdd binary AIGs converted from AAG
2019-02-08 Eddie HungRefactor to parse_aiger_header()
2019-02-08 Eddie HungAdd comment
2019-02-08 Eddie HungHandle reset logic in latches
2019-02-08 Eddie HungChange literal vars from int to unsigned
2019-02-08 Eddie HungCreate clk outside of latch loop
2019-02-08 Eddie HungHandle latch symbols too
2019-02-08 Eddie HungRemove return after log_error
2019-02-08 Eddie HungAdd support for symbol tables
2019-02-08 Eddie HungStub for binary AIGER
2019-02-07 David Shahfsm_opt: Fix runtime error for FSMs without a reset...
2019-02-06 Eddie HungCope WIDTH of ff/latch cells is default of zero
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie HungRemove check for cell->name[0] == '$'
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungRevert most of autotest.sh; for non *.v use Yosys to...
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr
2019-02-06 Eddie HungAdd INIT parameter to all ff/latch cells
2019-02-06 Eddie HungAdd tests for simple cases using defparam
2019-02-06 Eddie HungAdd -B option to autotest.sh to append to backend_opts
2019-02-06 Eddie HungExtend testcase
2019-02-06 Eddie HungAdd testcase
2019-02-06 Eddie HungRename ASCII tests
2019-02-06 Eddie HungWIP
2019-02-06 Clifford WolfAdd missing blackslash-to-slash convertion to smtio...
2019-02-05 Eddie HungAdd tests
2019-01-29 whitequarkwrite_verilog: correctly emit asynchronous transparent...
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t...
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword'
2019-01-27 Clifford WolfRemove asicworld tests for (unsupported) switch-level...
2019-01-27 whitequarkwrite_verilog: write $tribuf cell as ternary.
2019-01-27 whitequarkwrite_verilog: escape names that match SystemVerilog...
2019-01-25 David ShahMerge pull request #796 from whitequark/proc_clean_typo
2019-01-25 Miodrag MilanovicFixed Anlogic simulation model
2019-01-23 whitequarkproc_clean: fix critical typo.
2019-01-19 Clifford WolfMerge pull request #793 from whitequark/proc_clean_fix_...
2019-01-18 whitequarkproc_clean: fix fully def check to consider compare...
2019-01-17 Clifford WolfCleanups in igloo2 example design
2019-01-17 Clifford WolfAdd SF2 IO buffer insertion
2019-01-17 Clifford WolfImprove Igloo2 example
2019-01-17 Clifford WolfAdd "synth_sf2 -vlog", fix "synth_sf2 -edif"
2019-01-17 Clifford WolfAdd "write_edif -gndvccy"
2019-01-15 Clifford WolfAdd optional nullstr argument to log_id()
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end
2019-01-15 Clifford WolfMerge pull request #788 from whitequark/master
2019-01-15 Clifford WolfMerge pull request #787 from whitequark/flowmap_relax
2019-01-14 whitequarkmanual: document some gates.
2019-01-14 whitequarkmanual: explain $tribuf cell.
2019-01-08 Clifford WolfImprove igloo2 example
2019-01-08 whitequarkflowmap: clean up terminology.
2019-01-08 whitequarkflowmap: implement depth relaxation.
2019-01-07 Clifford WolfFix typo in manual
2019-01-07 Clifford WolfBugfix in $memrd sharing
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-07 Clifford WolfSwitch "bugpoint" from system() to run_command()
2019-01-07 Clifford WolfMerge pull request #783 from whitequark/bugpoint
2019-01-07 whitequarkbugpoint: new pass.
2019-01-06 whitequarkflowmap: construct a max-volume max-flow min-cut, not...
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-06 Scott MansellRename cells based on the wires they drive.
2019-01-05 Clifford WolfAdd skeleton Yosys-Libero igloo2 example project
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