yosys.git
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-09 Eddie HungFix comment
2019-12-07 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-07 Eddie HungMerge pull request #1555 from antmicro/fix-macc-xilinx...
2019-12-07 Eddie HungCall abc9 with "&write -n", and parse_xaiger() to cope
2019-12-07 Eddie HungRemove creation of $abc9_control_wire
2019-12-07 Eddie HungDo not connect undriven POs to 1'bx
2019-12-07 Eddie HungFix abc9 re-integration, remove abc9_control_wire,...
2019-12-07 Eddie HungFix writing non-whole modules, including inouts and...
2019-12-06 Jan Kowalewskitests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 Eddie Hungabc9 to use mergeability class to differentiate sync...
2019-12-06 Eddie Hungwrite_xaiger to support part-selected modules again
2019-12-06 Eddie Hungabc9 to do clock partitioning again
2019-12-06 Eddie HungRemove clkpart
2019-12-05 Eddie HungRevert "Special abc9_clock wire to contain only clock...
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell...
2019-12-05 Eddie HungMissing wire declaration
2019-12-05 Eddie Hungabc9_map.v to transform INIT=1 to INIT=0
2019-12-05 Eddie HungOh deary me
2019-12-05 Eddie HungBump ABC to get "&verify -s" fix
2019-12-05 Eddie Hungoutput reg Q -> output Q to suppress warning
2019-12-05 Eddie Hungabc9_map.v to do `zinit' and make INIT = 1'b0
2019-12-04 whitequarkkernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ...
2019-12-04 whitequarkmanual: document behavior of many comb cells more preci...
2019-12-04 Marcin Kościelnickixilinx: Add tristate buffer mapping. (#1528)
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping...
2019-12-04 Marcin Kościelnickixilinx: Add models for LUTRAM cells. (#1537)
2019-12-04 Eddie HungCleanup
2019-12-04 Eddie HungAdd assertion
2019-12-04 Eddie Hungwrite_xaiger to consume abc9_init attribute for abc9_flops
2019-12-04 Eddie HungAdd abc9_init wire, attach to abc9_flop cell
2019-12-03 Eddie HungRevert "Add INIT value to abc9_control"
2019-12-03 Eddie HungUpdate ABCREV for upstream bugfix
2019-12-03 Eddie Hungtechmap abc_unmap.v before xilinx_srl -fixed
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-03 Pepijn de Vosupdate test
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values
2019-12-02 Eddie HungAdd INIT value to abc9_control
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix
2019-12-02 Eddie HungCleanup
2019-12-02 Eddie HungUse pool instead of std::set for determinism
2019-12-02 Eddie HungUse pool<> not std::set<> for determinism
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds...
2019-12-01 David Shahabc9: Fix breaking of SCCs
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL.
2019-11-28 Eddie Hungclkpart -unpart into 'finalize'
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-28 Eddie HungMove \init signal for non-port signals as long as inter...
2019-11-28 Eddie HungRevert "Fold loop"
2019-11-27 Marcin Kościelnickiread_ilang: do bounds checking on bit indices
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungAdd multiple driver testcase
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungAdd comment, use sigmap
2019-11-27 Eddie HungRevert "Fold loop"
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie Hungean call after abc{,9}
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungDo not replace constants with same wire
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
2019-11-27 Eddie HungMerge pull request #1535 from YosysHQ/eddie/write_xaige...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/write_xaiger...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungCleanup
2019-11-27 Eddie HungCheck for nullptr
2019-11-27 Eddie HungStray log_dump
2019-11-27 Eddie HungRevert "submod to bitty rather bussy, for bussy wires...
2019-11-27 Eddie HungPromote output wires in sigmap so that can be detected
2019-11-27 Eddie HungFix wire width
2019-11-27 Eddie HungFix submod -hidden
2019-11-27 Eddie HungAdd -hidden option to submod
2019-11-27 Eddie HungNo need for -abc9
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells.
2019-11-27 Eddie Hunglatch -> box
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-27 Eddie HungAdd citation
2019-11-27 Eddie HungCheck for either sign or zero extension for postAdd...
2019-11-27 Eddie HungRemove notes
2019-11-27 Eddie HungFold loop
2019-11-27 Eddie HungDo not sigmap keep bits inside write_xaiger
2019-11-27 Eddie Hungxaiger: do not promote output wires
2019-11-27 Eddie HungAdd testcase derived from fastfir_dynamictaps benchmark
2019-11-27 Eddie Hungxaiger: do not promote output wires
2019-11-26 Eddie HungMove 'clean' from map_luts to finalize
2019-11-26 Eddie HungFix submod -hidden
2019-11-26 Eddie Hungclkpart to use 'submod -hidden'
2019-11-26 Eddie HungAdd -hidden option to submod
2019-11-26 Eddie HungUpdate docs with bullet points
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-26 Eddie HungMove \init from source wire to submod if output port
2019-11-26 Eddie HungAdd testcase where \init is copied
2019-11-25 Eddie HungFold loop
2019-11-25 Eddie HungDo not sigmap keep bits inside write_xaiger
2019-11-25 Eddie Hungclkpart to analyse async flops too
2019-11-25 Eddie HungFix debug
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