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yosys.git
2019-09-29
Miodrag Milanovic
Open aig frontend as binary file
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2019-09-29
Miodrag Milanović
Merge pull request #1413 from YosysHQ/mmicko/backend_bi...
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2019-09-29
Clifford Wolf
Merge pull request #1411 from aman-goel/YosysHQ-master
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2019-09-28
Miodrag Milanovic
Add aiger and protobuf backends binary support
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2019-09-28
Miodrag Milanovic
Support binary files for backends, fixes #1407
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2019-09-28
Eddie Hung
Fix box name
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2019-09-27
Aman Goel
Corrects btor2 backend
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2019-09-27
Marcin Kościelnicki
Fix _TECHMAP_REMOVEINIT_ handling.
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-27
Miodrag Milanović
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt...
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2019-09-27
Miodrag Milanovic
Change order of parameters, to work on other os
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2019-09-27
Clifford Wolf
Merge pull request #1404 from YosysHQ/fix_gzip_macos
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2019-09-26
Eddie Hung
Missing an '&'
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2019-09-26
Miodrag Milanovic
Make read/write gzip files on macos works, fixes #1357
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2019-09-25
Eddie Hung
Merge pull request #1401 from SergeyDegtyar/SergeyDegty...
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2019-09-25
SergeyDegtyar
Change sync controls to async.
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2019-09-25
Clifford Wolf
Merge pull request #1402 from YosysHQ/clifford/portlist
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2019-09-25
Clifford Wolf
Improve "portlist" command
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2019-09-24
Clifford Wolf
Add "portlist" command
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2019-09-24
SergeyDegtyar
adffs test update (equiv_opt -multiclock).
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2019-09-23
Miodrag Milanović
Merge pull request #1399 from nakengelhardt/fix-show...
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2019-09-23
N. Engelhardt
add xdot dependency to Brewfile
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2019-09-23
N. Engelhardt
fix show command for macos
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2019-09-21
Clifford Wolf
Merge pull request #1392 from YosysHQ/eddie/fix1391
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2019-09-21
Eddie Hung
Hell let's add the original #1381 testcase too
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2019-09-21
Eddie Hung
Revert abc9.cc
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2019-09-21
Eddie Hung
Add testcase
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2019-09-21
Eddie Hung
Trim mismatched connection to be same (smallest) size
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2019-09-21
Eddie Hung
Fix first testcase in #1391
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2019-09-20
Clifford Wolf
Merge pull request #1386 from YosysHQ/clifford/fix1360
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2019-09-20
Clifford Wolf
Fix handling of read_verilog config in AstModule::repro...
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2019-09-20
Clifford Wolf
Update CHANGELOG
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2019-09-20
Clifford Wolf
Add "add -mod"
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2019-09-20
Clifford Wolf
Merge pull request #1384 from YosysHQ/clifford/fix1381
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2019-09-19
Clifford Wolf
Add techmap_autopurge attribute, fixes #1381
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2019-09-19
Marcin Kościelnicki
Use extractinv for synth_xilinx -ise
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2019-09-19
Marcin Kościelnicki
Added extractinv pass
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2019-09-18
Eddie Hung
Document (* gentb_skip *) attr for test_autotb
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2019-09-18
Eddie Hung
Merge pull request #1355 from YosysHQ/eddie/peepopt_dff...
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2019-09-18
Eddie Hung
Merge pull request #1379 from mmicko/sim_models
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2019-09-18
Miodrag Milanovic
make note that it is for latch mode
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2019-09-18
Miodrag Milanovic
better lut handling
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2019-09-18
Miodrag Milanovic
better handling of lut and begin/end add
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2019-09-18
Clifford Wolf
Add "write_aiger -L"
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2019-09-18
Clifford Wolf
Fix stupid bug in btor back-end
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2019-09-16
Clifford Wolf
Bump version
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2019-09-16
Clifford Wolf
Merge pull request #1380 from YosysHQ/clifford/fix1372
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2019-09-16
Clifford Wolf
Fix handling of range selects on loop variables, fixes...
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2019-09-15
Eddie Hung
Merge pull request #1374 from YosysHQ/eddie/fix1371
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2019-09-15
Marcin Kościelnicki
xilinx: Make blackbox library family-dependent.
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2019-09-15
Clifford Wolf
Merge pull request #1377 from YosysHQ/clifford/fixzdigit
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2019-09-15
Miodrag Milanovic
Added simulation models for Efinix and Anlogic
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2019-09-14
Eddie Hung
Oops
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2019-09-13
Eddie Hung
Add counter-example from @cliffordwolf
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2019-09-13
Eddie Hung
Revert "Make one check $shift(x)? only; change testcase...
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2019-09-13
Eddie Hung
Spacing
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2019-09-13
Eddie Hung
Explicitly order function arguments
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2019-09-13
Eddie Hung
Use template specialisation
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2019-09-13
Eddie Hung
Revert "SigSet<Cell*> to use stable compare class"
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2019-09-13
Clifford Wolf
Fix handling of z_digit "?" and fix optimization of...
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2019-09-13
Clifford Wolf
Merge pull request #1373 from YosysHQ/clifford/fix1364
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2019-09-13
Clifford Wolf
Fix lexing of integer literals without radix
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2019-09-12
Eddie Hung
Grammar
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2019-09-12
Eddie Hung
static_assert to enforce this going forward
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2019-09-12
Eddie Hung
SigSet<Cell*> to use stable compare class
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2019-09-12
David Shah
Merge pull request #1370 from YosysHQ/dave/equiv_opt_mu...
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2019-09-12
Clifford Wolf
Fix lexing of integer literals, fixes #1364
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2019-09-11
Eddie Hung
Tidy up
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2019-09-11
Eddie Hung
Fix UB
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2019-09-11
Eddie Hung
Cope with presence of reset muxes too
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2019-09-11
Eddie Hung
Cleanup
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2019-09-11
Eddie Hung
Add more tests
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2019-09-11
Eddie Hung
Only display log message if did_something
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2019-09-11
Marcin Kościelnicki
Add -match-init option to dff2dffs.
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2019-09-11
David Shah
Add equiv_opt -multiclock
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2019-09-11
David Shah
Merge pull request #1362 from xobs/smtbmc-msvc2-build...
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2019-09-11
Eddie Hung
Rename dffmuxext -> dffmux, also remove constants in...
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2019-09-11
Eddie Hung
proc instead of prep
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2019-09-11
Eddie Hung
Add unsigned case
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2019-09-10
Clifford Wolf
Bump version
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2019-09-10
Sean Cross
tests: ice40: fix div_mod SB_LUT4 count
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2019-09-09
Eddie Hung
Fix misspelling
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2019-09-09
Sean Cross
passes: opt_share: don't statically initialize mergeabl...
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2019-09-08
Sean Cross
msys2: launcher: fix warnings and errors under g++
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2019-09-08
Sean Cross
backends: smt2: use $(CXX) variable for compiler
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2019-09-07
Marcin Kościelnicki
synth_xilinx: Support init values on Spartan 6 flip...
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2019-09-07
Marcin Kościelnicki
techmap: Add support for extracting init values of...
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2019-09-07
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-09-07
Eddie Hung
Add missing -assert to equiv_opt
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2019-09-07
Eddie Hung
Missing equiv_opt -assert
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2019-09-07
Eddie Hung
Make one check $shift(x)? only; change testcase to...
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2019-09-07
Eddie Hung
Usee equiv_opt -assert
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2019-09-05
Eddie Hung
Merge pull request #1312 from YosysHQ/xaig_arrival
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2019-09-05
Clifford Wolf
Bump version
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2019-09-05
Clifford Wolf
Merge pull request #1350 from YosysHQ/clifford/fixsby59
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2019-09-05
Clifford Wolf
Merge pull request #1330 from YosysHQ/clifford/fix1145
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2019-09-05
Eddie Hung
simple/peepopt.v tests to various/peepopt.ys with equiv...
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2019-09-05
Eddie Hung
Revert "abc9 followed by clean otherwise netlist could...
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2019-09-05
Clifford Wolf
Update README.md
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2019-09-05
Clifford Wolf
Rename conflicting wires on flatten/techmap, add "hierc...
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