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gram.git
2020-07-03
Jean THOMAS
Fix permissions for simulation script
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2020-07-03
Jean THOMAS
Add simulation script into SourceHut builds
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2020-07-03
Jean THOMAS
Exclude DDRDLLA from tree
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2020-07-03
Jean THOMAS
Ensure dramsync runs at 100Mhz, sync2x at 200Mhz
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2020-07-03
Jean THOMAS
Remove DDRDLLA
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2020-07-03
Jean THOMAS
Add build script for SourceHut
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2020-07-03
Jean THOMAS
Add tests in DFI Injector for odt and reset signals
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2020-07-03
Jean THOMAS
Check for additional signals in phase injector at t=0
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2020-07-03
Jean THOMAS
Add DFI injector test case
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2020-07-03
Jean THOMAS
Update simulation gitignore
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2020-07-03
Jean THOMAS
Update gram simulation documentation
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2020-07-03
Jean THOMAS
Add cleaning pass
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2020-07-03
Jean THOMAS
Fix autopep8 madness
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2020-07-03
Jean THOMAS
Rework CRG simulation
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2020-07-03
Jean THOMAS
Externalize CRG into its own file
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2020-07-03
Jean THOMAS
Add devel doc
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2020-07-03
Jean THOMAS
Add test for Refresher
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2020-07-03
Jean THOMAS
Refactor generic_test execution
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2020-07-03
Jean THOMAS
Use spaces for indentation
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2020-07-03
Jean THOMAS
Add tests for core/refresher.py
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2020-07-03
Jean THOMAS
Removing reset=0 attribute as it is already the default...
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2020-07-02
Jean THOMAS
Use reset signal from dramsync instead of sync
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2020-07-02
Jean THOMAS
Make RefreshPostponer more similar to LiteDRAM's
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2020-07-02
Jean THOMAS
Fix RefreshPostponer output stuck to 1
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2020-07-02
Jean THOMAS
Flatten specific parts of the designs
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2020-07-02
Jean THOMAS
Add missing command issue strobe for ZQ calibration
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2020-07-02
Jean THOMAS
Remove PyYAML dependency
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2020-07-02
Jean THOMAS
Fix register addresses, add missing command_issue strobe
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2020-07-02
Jean THOMAS
Set names to prevent CSR/DomainRenamer incompatibility
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2020-07-02
Jean THOMAS
Add DDRDLLA patch
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2020-07-01
Jean THOMAS
Fix merge
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2020-07-01
Jean THOMAS
Rework indentation and add Wishbone tests
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2020-07-01
Jean THOMAS
Add Wishbone interaction code
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2020-07-01
Jean THOMAS
Add Wishbone interaction code
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2020-07-01
Jean THOMAS
Fix Iverilog simulation
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2020-07-01
Jean THOMAS
Generate ilang file
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2020-06-30
Jean THOMAS
Build nMigen gateware in a specific folder
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2020-06-30
Jean THOMAS
Remove LED code in CRG
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2020-06-30
Jean THOMAS
Remove Minerva dependency
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2020-06-30
Jean THOMAS
Applying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy...
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2020-06-29
Jean THOMAS
Define simulation time as a parameter
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2020-06-29
Jean THOMAS
Define PLL's PHASELOADREG input
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2020-06-29
Jean THOMAS
Use -n option in vvp to enable CTRL+C
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2020-06-29
Jean THOMAS
Fix PLL instanciation code for CRG simulation
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2020-06-29
Jean THOMAS
Dump whole module
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2020-06-29
Jean THOMAS
Fix DQSBUFM floating DYNDELAY
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2020-06-29
Jean THOMAS
Set DRAM's CK_N to low
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2020-06-29
Jean THOMAS
Fix autopep8 madness
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2020-06-29
Jean THOMAS
Use BB instead of TRELLIS_IO
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2020-06-29
Jean THOMAS
Fix CRG, revert to resetful sync domain
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2020-06-29
Jean THOMAS
Set UART RX to 1'b1
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2020-06-29
Jean THOMAS
Add -Wall to simulations
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2020-06-26
Jean THOMAS
Add testbench for SoC simulation
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2020-06-26
Jean THOMAS
Use FST instead of VCD
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2020-06-26
Jean THOMAS
Exclude .fst files
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2020-06-26
Jean THOMAS
Add DDRSoC simulation
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2020-06-26
Jean THOMAS
Add gitignore for simulation folder
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2020-06-26
Jean THOMAS
Fix PLL code
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2020-06-26
Jean THOMAS
Add DRAM model
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2020-06-25
Jean THOMAS
Fix typo
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2020-06-25
Jean THOMAS
Add simulation code
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2020-06-25
Jean THOMAS
Add README.md for gram tests
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2020-06-25
Jean THOMAS
Add rddata_en, wrdata_mask tests
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2020-06-25
Jean THOMAS
Add wrdata, wrdata_en tests to Phase Injector unit...
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2020-06-25
Jean THOMAS
Fix R/W permissions to the bare minimum
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2020-06-25
Jean THOMAS
Set UART bridge SEL signals to 0xF
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2020-06-25
Jean THOMAS
Add Wishbone read/write helpers
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2020-06-25
Jean THOMAS
Use constants for CSR addresses
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2020-06-25
Jean THOMAS
Add bank address test
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2020-06-25
Jean THOMAS
Fix DFII testing, test address set
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2020-06-24
Jean THOMAS
Add buggy test for DFII
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2020-06-24
Jean THOMAS
Fix CSR issue in PhaseInjector (r_data used for reading...
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2020-06-24
Jean THOMAS
Fix CSR issue in DFII (r_data used for reading host...
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2020-06-24
Jean THOMAS
Simply arbiter when there is only 1 request to arbitrate
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2020-06-24
Jean THOMAS
Ensure we have at least one master
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2020-06-23
Jean THOMAS
Only declare wants_zqcs signal if needed
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2020-06-23
Jean THOMAS
Simplify connections from refreshers to IOs (not FSM...
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2020-06-23
Jean THOMAS
Refactor test code
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2020-06-23
Jean THOMAS
Fix DFII bitfield constants
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2020-06-23
Jean THOMAS
Fix public libgram header
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2020-06-23
Jean THOMAS
Compile libgram as C99 code
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2020-06-23
Jean THOMAS
Fix typo in GramWidth enum declaration
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2020-06-23
Jean THOMAS
Fix ZQCSExecuter (set a signal to the proper size)...
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2020-06-23
Jean THOMAS
Refresher: fix a address size (fixes #14)
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2020-06-22
Jean THOMAS
Remove shadowing statement
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2020-06-22
Jean THOMAS
Replace bits_for with range
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2020-06-22
Jean THOMAS
Remove code for hybrid formal proof, unused
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2020-06-22
Jean THOMAS
Rollback to the ECP5 P/N used in ECPIX-5
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2020-06-22
Jean THOMAS
Fix pinout
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2020-06-22
Jean THOMAS
Use TRELLIS_IO instead of BB in ECP5 PHY
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2020-06-19
Jean THOMAS
Update memtest code in libgram
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2020-06-19
Jean THOMAS
Remove tests from gram.compat
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2020-06-19
Jean THOMAS
Move tests to a dedicated folder
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2020-06-18
Jean THOMAS
Add unit tests for delayed_enter
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2020-06-18
Jean THOMAS
Add test case for delayed_enter
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2020-06-18
Jean THOMAS
Use BB instance for bidirectionnal IOs
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2020-06-17
Jean THOMAS
Remove lambdasoc dependency from UARTBridge
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2020-06-17
Jean THOMAS
Rollback PHY changes, use raw pins
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2020-06-16
Jean THOMAS
Partially fix the tristate IOs on DDR3 RAM
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2020-06-16
Jean THOMAS
Fix oMigen cases and resource syntax
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