yosys.git
2018-12-07 David ShahMerge pull request #727 from whitequark/opt_lut
2018-12-07 whitequarkopt_lut: leave intact LUTs with cascade feeding module...
2018-12-07 whitequarkopt_lut: show original truth table for both cells.
2018-12-07 whitequarkopt_lut: add -limit option, for debugging misoptimizations.
2018-12-06 Clifford WolfAdd missing .gitignore
2018-12-06 Clifford WolfBugfix in opt_expr handling of a<0 and a>=0
2018-12-06 Clifford WolfVerific updates
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut
2018-12-05 whitequarksynth_ice40: add -noabc option, to use built-in LUT...
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to...
2018-12-05 whitequarkFix typo.
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support
2018-12-05 Clifford WolfRename opt_lut.cpp to opt_lut.cc
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut
2018-12-05 Clifford WolfMerge pull request #716 from whitequark/ice40_unlut
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such...
2018-12-05 whitequarkopt_lut: always prefer to eliminate 1-LUTs.
2018-12-05 whitequarkopt_lut: collect and display statistics.
2018-12-05 whitequarkopt_lut: refactor to use a worker. NFC.
2018-12-05 whitequarksynth_ice40: add -relut option, to run ice40_unlut...
2018-12-05 whitequarkopt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 whitequarkExtract ice40_unlut pass from ice40_opt.
2018-12-05 Serge BazanskiMerge pull request #719 from YosysHQ/q3k/flailing-aroun...
2018-12-05 Sergiusz Bazanskitravis/osx: fix, use clang instead of gcc
2018-12-04 Clifford WolfFix typo
2018-12-04 Clifford WolfMerge pull request #702 from smunaut/min_ce_use
2018-12-04 Diego HChanges in GoWin synth commands and ALU primitive support
2018-12-02 Miodrag MilanovicLeave only real black box cells
2018-12-01 Miodrag MilanovicInitial support for Anlogic FPGA
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-29 Clifford WolfImprove ConstEval error handling for non-eval cell...
2018-11-27 Sylvain Munautice40: Add option to only use CE if it'd be use by...
2018-11-27 Sylvain Munautdff2dffe: Add option for unmap to only remove DFFE...
2018-11-24 Sylvain MunautMake return value of $clog2 signed
2018-11-20 Clifford WolfAdd iteration limit to "opt_muxtree"
2018-11-13 Clifford WolfUpdate ABC to git rev 2ddc57d
2018-11-12 Clifford WolfAdd "write_aiger -I -O -B"
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-11 Clifford WolfUpdate ABC to git rev 68da3cf
2018-11-10 Eddie HungAdd support for Xilinx PS7 block
2018-11-09 Clifford WolfSet Verific flag vhdl_support_variable_slice=1
2018-11-09 David Shahecp5: Add 'fake' DCU parameters
2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells
2018-11-09 Clifford WolfMerge pull request #696 from arjenroodselaar/verific_darwin
2018-11-08 Clifford WolfFix "make ystests" to use correct Yosys binary
2018-11-08 Arjen RoodselaarUse appropriate static libraries when building with...
2018-11-07 Clifford WolfMerge pull request #693 from YosysHQ/rlimit
2018-11-07 David Shahecp5: Adding some blackbox cells
2018-11-07 Clifford WolfLimit stack size to 16 MB on Darwin
2018-11-06 Clifford WolfMerge pull request #694 from trcwm/dffmap_expr_fix
2018-11-06 Niels MoseleyDFFLIBMAP: changed 'missing pin' error into a warning...
2018-11-06 Clifford WolfRun solver in non-incremental mode whem smtio.py is...
2018-11-06 Clifford WolfUpdate ABC rev to 4d56acf
2018-11-06 Clifford WolfFix for improved smtio.py rlimit code
2018-11-06 Clifford WolfImprove stack rlimit code in smtio.py
2018-11-05 Clifford WolfAllow square brackets in liberty identifiers
2018-11-05 Clifford WolfMerge pull request #691 from arjenroodselaar/stacksize
2018-11-05 Arjen RoodselaarUse conservative stack size for SMT2 on MacOS
2018-11-04 Clifford WolfAdd warning for SV "restrict" without "property"
2018-11-04 Clifford WolfAdd proper error message for when smtbmc "append" fails
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-11-04 Clifford WolfMerge pull request #687 from trcwm/master
2018-11-04 Clifford WolfMerge pull request #688 from ZipCPU/rosenfell
2018-11-03 ZipCPUMake and dependent upon LSB only
2018-11-03 Niels MoseleyLiberty file newline handling is more relaxed. More...
2018-11-03 Niels MoseleyReport an error when a liberty file contains pin refere...
2018-11-01 Clifford WolfDo not generate "reg assigned in a continuous assignmen...
2018-11-01 Clifford WolfAdd support for signed $shift/$shiftx in smt2 back-end
2018-10-31 Clifford WolfMerge branch 'igloo2'
2018-10-31 Clifford WolfFix sf2 LUT interface
2018-10-31 Clifford WolfBasic SmartFusion2 and IGLOO2 synthesis support
2018-10-30 Clifford WolfMerge pull request #680 from jburgess777/fix-empty...
2018-10-28 Jon BurgessAvoid assert when label is an empty string
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfFix minor typo in error message
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the...
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-22 whentzefix unhandled std::out_of_range when calling yosys...
2018-10-22 David Shahecp5: Remove DSP parameters that don't work
2018-10-21 rafaeltpusing [i] to access individual bits of SigSpec and...
2018-10-21 David Shahecp5: Add DSP blackboxes
2018-10-21 rafaeltpcleaning up for PR
2018-10-21 rafaeltpfixing code style
2018-10-21 rafaeltpsolves #675
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the...
2018-10-20 Ruben UndheimFixed memory leak
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve
2018-10-19 David Shahecp5: Sim model fixes
2018-10-19 David Shahecp5: Add latch inference
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-19 David Shahmemory_bram: Reset make_outreg when growing read ports
next