openpower-isa.git
2022-01-18 Jacob Lifshayadd log2 pseudo-code helper
2022-01-18 Jacob Lifshayformat code
2022-01-18 Jacob Lifshayadd test_caller_logical.py
2022-01-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-soc.org:922...
2022-01-18 Jacob Lifshayspeed up pywriter
2022-01-17 Luke Kenneth... add a couple of trap pipeline unit tests
2022-01-17 Jacob LifshayWIP speed up pywriter by caching stuff more and not...
2022-01-16 Dmitry Selyutinsv_binutils: fix typo in disclaimer
2022-01-16 Dmitry Selyutinsv_binutils: add missing include directives
2022-01-16 Dmitry Selyutinsv_binutils: introduce SVP64 entries
2022-01-16 Dmitry Selyutinsv_binutils: rename Field into CType
2022-01-16 Dmitry Selyutinsv_binutils: inherit Entry from Field
2022-01-16 Dmitry Selyutinsv_binutils: drop semicolons in c_var methods
2022-01-15 Luke Kenneth... correctly identify atomic reservation CSV file field and
2022-01-15 Luke Kenneth... add atomic reservation field to Power Decoder data...
2022-01-14 Jacob Lifshayremove stray newline
2022-01-14 Jacob Lifshayadd grev[w][i][.] pseudo-code
2022-01-12 Luke Kenneth... add second version of wb_get which can cope with pipelines
2022-01-10 Luke Kenneth... increase addr_wid to 64 in TestRunnerBase. hm this...
2022-01-10 Luke Kenneth... enable privileged-instruction detection which had previ...
2022-01-09 Dmitry Selyutinsv_binutils: drop redundant imports
2022-01-09 Dmitry Selyutinsv_binutils: sort entries by name
2022-01-09 Dmitry Selyutinsv_binutils: discard VHDL stuff in comments
2022-01-09 Dmitry Selyutinsv_binutils: calculate reserved bits
2022-01-09 Dmitry Selyutinsv_binutils: reorder declarations
2022-01-09 Dmitry Selyutinsv_binutils: print opcode as hexadecimal
2022-01-06 Jacob Lifshayadd grev[w][i] instructions
2022-01-06 Jacob Lifshayformat code
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2022-01-06 Luke Kenneth... add tlbsync and wait as NOPs
2022-01-05 Luke Kenneth... add eieio instruction as a NOP to minor 31 csv
2022-01-05 Luke Kenneth... add lbzcix instruction which had been completely forgot...
2022-01-05 Dmitry Selyutinsv_binutils: introduce real opcode class
2022-01-05 Dmitry Selyutinsv_binutils: parse CSVs directly
2022-01-05 Dmitry Selyutinsv_binutils: support basic header generation
2022-01-05 Dmitry Selyutinsv_binutils: introduce code generator class
2022-01-05 Dmitry Selyutinsv_binutils: use stdin as input stream
2022-01-05 Dmitry Selyutinsv_binutils: introduce helper classes
2022-01-03 Luke Kenneth... copy over msr and rename cia to nia in PowerDecoder2
2021-12-28 Cesar StraussAdd an inorder flag to pspec
2021-12-27 Luke Kenneth... add empty default_mem for running without MMU
2021-12-27 Luke Kenneth... whoops wrong parameter name
2021-12-27 Luke Kenneth... quick attempt to fix test_decoder_gas.py (did not work)
2021-12-27 Mikolaj Wielgusbool() is !!() for integers
2021-12-27 Mikolaj WielgusAdd missing parentheses for explicit operator precedence
2021-12-26 Luke Kenneth... add very basic PowerDecode2 test which at least gets...
2021-12-26 Luke Kenneth... a few extra things discovered needing c syntax not...
2021-12-26 Mikolaj WielgusGive human-readable names to slots, run functions and...
2021-12-25 Mikolaj WielgusPut CRTL CFFI modules in crtl dir
2021-12-25 Dmitry Selyutinsv_binutils: provide small comment on regex
2021-12-25 Dmitry Selyutinsv_binutils: introduce entry dataclass
2021-12-24 Luke Kenneth... clear memory is optional
2021-12-24 Luke Kenneth... whoops forgot to put the copy of the wb_get memory...
2021-12-23 Luke Kenneth... code cleanup / comments
2021-12-23 Luke Kenneth... repeat power decode test to check performance
2021-12-23 Luke Kenneth... bit of a tidyup of crtl:
2021-12-23 Luke Kenneth... add load-store byte-reverse 64-bit unit test
2021-12-23 Mikolaj WielgusAdd CRTL templates
2021-12-23 Mikolaj WielgusGive unique names to CRTL-generated modules
2021-12-23 Mikolaj WielgusMove "pending" set to C
2021-12-22 Mikolaj WielgusMake _PySignalState CRTL-aware
2021-12-21 Luke Kenneth... take a copy of the wb_get memory and then for each...
2021-12-21 Luke Kenneth... ISACaller (actually RADIXMMU) only do virtual memory...
2021-12-20 Mikolaj WielgusGenerate variable declaration in some missing places
2021-12-20 Luke Kenneth... create header/footer for crtl code-generation
2021-12-20 Luke Kenneth... whoops forgot to trap if non-execute (instruction)...
2021-12-19 Luke Kenneth... TODO notes for executing ISACaller Invalid Instruction...
2021-12-19 Luke Kenneth... pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
2021-12-19 Luke Kenneth... add "stop at pc" argument to TestCase,
2021-12-19 Dmitry Selyutinsv/binutils.py: provide sketch sv_decode.vhdl converter
2021-12-19 Luke Kenneth... save mmu simulation to different gtkwave file in TestRu...
2021-12-18 Luke Kenneth... bit more verbose info about number of instructions run
2021-12-18 Luke Kenneth... use new core domain variable in TestRunnerBase
2021-12-18 Luke Kenneth... update comments in wb_get
2021-12-18 Luke Kenneth... ooo annoying, it is actually icache.ibus
2021-12-18 Luke Kenneth... whoops error in accessing icache.ibus which is an inter...
2021-12-17 Mikolaj WielgusCall the simulator-generated C using the CFFI
2021-12-16 Luke Kenneth... bug where t1 was set to zero but s2 was not in imdct36_...
2021-12-16 Luke Kenneth... start/stop wb_get in TestRunnerBase, otherwise it never...
2021-12-15 Luke Kenneth... must read off of ibus in wb_get TestRunnerBase
2021-12-14 Mikolaj WielgusAdd CFFI as dependency
2021-12-13 Tobias Platenadd namedtuple MSRSpec
2021-12-12 Luke Kenneth... copy over fake OP_FETCH_FAILED and instruction on...
2021-12-12 Luke Kenneth... enable mmu_cache_wb for wb_get mode in TestRunnerBase
2021-12-12 Luke Kenneth... add pretty-print of MMU memory to be used for a TestRun...
2021-12-11 Luke Kenneth... remove ROTL64(1, idx), just use TLI[7-idx] it is shorte...
2021-12-11 Luke Kenneth... use concat in ternlogi to reduce code size
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm
2021-12-10 Jacob Lifshayformat code
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-10 Jacob Lifshayadd .gitignore to ignore the generated vhdl
2021-12-09 Luke Kenneth... add I-Cache wishbone bus to wb_get when MMU and ROM...
2021-12-09 Luke Kenneth... add warning about creation of "-.csv" which indicates...
2021-12-09 Luke Kenneth... add FAST SPRs temporarily to power_enums
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-12-08 Luke Kenneth... add instr_fault to PowerDecoder2
2021-12-08 Luke Kenneth... whitespace
2021-12-08 Luke Kenneth... code-comments for LDSTException.instr_fault
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