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yosys.git
2021-08-01
Marcelina Kościelnicka
memory_bram: Some refactoring
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2021-07-31
github-actions...
Bump version
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2021-07-30
Miodrag Milanović
Update version.yml
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2021-07-30
Maciej Dudek
Fixes xc7 BRAM36s
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2021-07-30
Zachary Snow
proc_rmdead: use explicit pattern set when there are...
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2021-07-30
Zachary Snow
genrtlil: add width detection for AST_PREFIX nodes
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2021-07-30
github-actions...
Bump version
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2021-07-29
Marcelina Kościelnicka
opt_lut: Allow more than one -dlogic per cell type.
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2021-07-29
Zachary Snow
verilog: save and restore overwritten macro arguments
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2021-07-29
github-actions...
Bump version
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2021-07-28
Marcelina Kościelnicka
verilog: Emit $meminit_v2 cell.
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2021-07-28
Marcelina Kościelnicka
backends/verilog: Support meminit with mask.
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2021-07-28
Marcelina Kościelnicka
memory: Introduce $meminit_v2 cell, with EN input.
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2021-07-28
github-actions...
Bump version
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2021-07-27
Marcelina Kościelnicka
proc: Run opt_expr at the end
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2021-07-27
Marcelina Kościelnicka
opt_expr: Propagate constants to port connections.
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2021-07-27
github-actions...
Bump version
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2021-07-26
Miodrag Milanovic
Add version bump workflow
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2021-07-21
Miodrag Milanovic
Update to latest verific
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2021-07-20
Rupert Swarbrick
Use new read_id_num helper function elsewhere in hierar...
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2021-07-20
Rupert Swarbrick
Extract connection checking logic from expand_module...
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2021-07-20
whitequark
Merge pull request #2885 from whitequark/cxxrtl-fix...
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2021-07-20
whitequark
Merge pull request #2884 from whitequark/cxxrtl-fix...
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2021-07-20
whitequark
cxxrtl: treat wires with multiple defs as not inlinable.
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2021-07-20
whitequark
cxxrtl: treat assignable internal wires used only for...
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2021-07-20
whitequark
Merge pull request #2881 from whitequark/cxxrtl-sideway...
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2021-07-19
whitequark
cxxrtl: escape colon in variable names in VCD writer.
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2021-07-18
whitequark
Merge pull request #2880 from whitequark/cxxrtl-fix...
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2021-07-18
whitequark
cxxrtl: add debug_item::{get,set}.
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2021-07-17
whitequark
Merge pull request #2879 from whitequark/cxxrtl-fix...
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2021-07-17
whitequark
cxxrtl: treat internal wires used only for debug as...
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2021-07-16
Rupert Swarbrick
Add support for parsing the SystemVerilog 'bind' construct
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2021-07-16
whitequark
Merge pull request #2874 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
Merge pull request #2873 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
Merge pull request #2872 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
cxxrtl: run hierarchy pass regardless of (*top*) attrib...
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2021-07-16
whitequark
cxxrtl: emit debug items for unused public wires.
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2021-07-16
whitequark
cxxrtl: don't expect user cell inputs to be wires.
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2021-07-16
whitequark
Merge pull request #2871 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
cxxrtl: don't mark buffered internal wires as UNUSED...
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2021-07-16
whitequark
Merge pull request #2870 from whitequark/cxxrtl-fix...
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2021-07-15
whitequark
cxxrtl: mark dead local wires as unused even with inlin...
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2021-07-15
Zachary Snow
sv: fix two struct access bugs
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2021-07-15
Rupert Swarbrick
Add a test for interfaces on modules loaded on-demand
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2021-07-15
Rupert Swarbrick
Extract missing module support in hierarchy.cc to a...
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2021-07-14
whitequark
Merge pull request #2866 from rswarbrick/found-init
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2021-07-14
Rupert Swarbrick
Delete unused found_init variable
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2021-07-13
Marcelina Kościelnicka
kernel/mem: Add a coalesce_inits helper.
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2021-07-12
GCHQDeveloper560
Add support for the Bitwuzla solver
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Use delayed removal for inits as well.
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Add documentation for more helper functions.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Support memory writes in processes.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Add support for memory read port reset.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Add support for mem read port initial data.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Convert to Mem helpers.
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Commit new values of attributes in emit.
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Make the Mem helpers inherit from AttrObject.
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2021-07-11
Marcelina Kościelnicka
rtlil: Make Process handling more uniform with Cell...
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2021-07-10
Marcelina Kościelnicka
ice40: Fix LUT input indices in opt_lut -dlogic (again).
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2021-07-09
Miodrag Milanovic
Update to latest Verific with extensions for initial...
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2021-07-06
Zachary Snow
sv: fix a few struct and enum memory leaks
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2021-07-06
gatecat
ecp5: Add DCSC blackbox
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2021-07-05
Claire Xen
Merge pull request #2835 from YosysHQ/verific_command
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2021-07-05
Xiretza
Makefile: allow running multiple sanitizers at once
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2021-07-05
Xiretza
Makefile: use git/make -C instead of cd
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2021-07-05
Xiretza
Makefile: pass PRETTY=0 to ABC
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2021-07-05
Xiretza
Makefile: don't bake DESTDIR into libyosys DT_SONAME
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2021-07-05
Xiretza
Makefile: clean up PYOSYS configuration
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2021-07-05
Miodrag Milanovic
Add additional help
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2021-06-19
whitequark
Merge pull request #2842 from whitequark/fix-wasi-build
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2021-06-19
whitequark
Fix WASI build after commit 1d88bea1.
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2021-06-18
Miodrag Milanović
Merge pull request #2836 from YosysHQ/gatecat/pyosys...
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2021-06-17
Rupert Swarbrick
Move interface expansion in hierarchy.cc into a helper...
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2021-06-17
Zachary Snow
sv: fix up end label checking
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2021-06-16
Ashton Snelgrove
Include blif reader header in public facing extension...
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2021-06-16
gatecat
pyosys: Clear SIGINT handler after Python loads
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2021-06-16
Miodrag Milanovic
Support command files in Verific
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2021-06-14
Xiretza
verilog: fix leaking of type names in parser
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2021-06-14
Xiretza
verilog: fix wildcard port connections leaking memory
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2021-06-14
Xiretza
ast: delete wires and localparams after finishing const...
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2021-06-14
Xiretza
verilog: fix leaking ASTNodes
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2021-06-14
Xiretza
ast: fix error condition causing assert to fail
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2021-06-14
Zachary Snow
macos: fix leak in proc_self_dirname()
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2021-06-14
Rupert Swarbrick
Simplify some RTLIL destructors
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2021-06-14
Marcelina Kościelnicka
verilog: Squash a memory leak.
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2021-06-11
Marcelina Kościelnicka
Add regression test for #2824.
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2021-06-11
gatecat
opt_muxtree: Update port_off and port_idx even for...
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2021-06-09
Marcelina Kościelnicka
opt_expr: Fix mul/div/mod by POT patterns to support...
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2021-06-09
Marcelina Kościelnicka
opt_expr: Optimize div/mod by const 1.
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2021-06-09
Claire Xen
Merge pull request #2817 from YosysHQ/claire/fixemails
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2021-06-09
Claire Xenia...
Fix deadname SVN links
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2021-06-09
Claire Xenia...
Intersynth URL
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2021-06-09
Claire Xenia...
More deadname stuff
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2021-06-09
Claire Xenia...
Fix icestorm links
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2021-06-09
Claire Xenia...
More deadname stuff
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2021-06-09
Claire Xenia...
Use HTTPS for website links, gatecat email
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2021-06-09
Claire Xenia...
Fix files with CRLF line endings
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2021-06-08
Zachary Snow
verilog: check for module scope identifiers during...
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2021-06-08
Zachary Snow
mem2reg: tolerate out of bounds constant accesses
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2021-06-08
Zachary Snow
autoname: simple perf optimizations
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