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yosys.git
2021-02-23
William D....
machxo2: Add add_sub test. Fix tests to include FACADE_...
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2021-02-23
William D....
machxo2: Add -noiopad option to synth_machxo2.
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2021-02-23
William D....
machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
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2021-02-23
William D....
machxo2: Fix cells_sim typo where OFX1 was multiply...
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2021-02-23
William D....
machxo2: synth_machxo2 now maps ports to FACADE_IO.
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2021-02-23
William D....
machxo2: Add initial value for Q in FACADE_FF.
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2021-02-23
William D....
machxo2: Add FACADE_IO simulation model. More comments...
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2021-02-23
William D....
machxo2: Add FACADE_SLICE simulation model.
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2021-02-23
William D....
machxo2: Improve FACADE_FF simulation model.
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2021-02-23
William D....
machxo2: Improve LUT4 techmap. Use same output port...
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2021-02-23
William D....
machxo2: Add dffe test.
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2021-02-23
William D....
machxo2: Add dff.ys test, fix another cells_map.v typo.
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2021-02-23
William D....
machxo2: Fix more oversights in machxo2 models. logic...
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2021-02-23
William D....
machxo2: Add test/arch/machxo2 directory (test does...
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2021-02-23
William D....
machxo2: Fix typos. test/arch/run-test.sh passes.
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2021-02-23
William D....
machxo2: Create basic techlibs and synth_machxo2 pass.
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2021-02-22
Karol Gugala
frontend: json: parse negative values
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2021-02-22
Marcelina Kościelnicka
assertpmux: Fix crash on unused $pmux output.
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2021-02-21
whitequark
Merge pull request #2586 from zachjs/tern-recurse
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2021-02-21
whitequark
Merge pull request #2591 from zachjs/verilog-preproc...
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2021-02-19
Zachary Snow
verilog: error on macro invocations with missing argume...
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2021-02-18
Yosys Bot
Bump version
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2021-02-17
Claire Xen
Merge pull request #2590 from RobertBaruch/fix_fast_sop...
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2021-02-17
Robert Baruch
Fixes command line for abc pass in -fast -sop mode
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2021-02-16
Yosys Bot
Bump version
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2021-02-15
Claire Xen
Merge pull request #2574 from dh73/master
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2021-02-13
Yosys Bot
Bump version
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2021-02-12
Zachary Snow
verilog: support recursive functions using ternary...
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2021-02-12
gatecat
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct
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2021-02-12
Miodrag Milanovic
Ganulate Verific support
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2021-02-12
Yosys Bot
Bump version
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2021-02-11
whitequark
Merge pull request #2573 from zachjs/repeat-call
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2021-02-11
Zachary Snow
Merge pull request #2578 from zachjs/genblk-port
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2021-02-11
Zachary Snow
Merge pull request #2584 from antmicro/atom_type_signedness
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2021-02-11
Kamil Rakoczy
Add missing is_signed to type_atom
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2021-02-07
Zachary Snow
verlog: allow shadowing module ports within generate...
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2021-02-07
Yosys Bot
Bump version
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2021-02-06
whitequark
Merge pull request #2576 from zachjs/port-bind-sign...
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2021-02-06
Zachary Snow
genrtlil: fix signed port connection codegen failures
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2021-02-06
Yosys Bot
Bump version
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2021-02-05
whitequark
Merge pull request #2572 from antmicro/check-labels
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2021-02-05
Yosys Bot
Bump version
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2021-02-04
Diego H
Accept disable case for SVA liveness properties.
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2021-02-04
Kamil Rakoczy
Add check of begin/end labels for genblock
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2021-02-04
Zachary Snow
verilog: refactored constant function evaluation
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2021-02-04
whitequark
Merge pull request #2529 from zachjs/unnamed-genblk
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2021-02-04
Yosys Bot
Bump version
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2021-02-03
whitequark
Merge pull request #2436 from dalance/fix_generate
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2021-01-31
Zachary Snow
verilog: significant block scoping improvements
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2021-01-31
Yosys Bot
Bump version
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2021-01-30
Miodrag Milanovic
Require latest Verific build
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2021-01-30
Yosys Bot
Bump version
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2021-01-29
Marcelina Kościelnicka
ast: fix dump_vlog display of casex/casez
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2021-01-29
whitequark
Merge pull request #2564 from whitequark/flatten-improv...
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2021-01-29
Yosys Bot
Bump version
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2021-01-28
whitequark
Merge pull request #2569 from zachjs/macro-arg-surround...
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2021-01-28
Claire Xen
Merge pull request #2535 from Ravenslofty/scc-specify
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2021-01-28
Zachary Snow
verilog: strip leading and trailing spaces in macro...
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2021-01-27
Yosys Bot
Bump version
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2021-01-26
Marcelina Kościelnicka
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-26
Marcelina Kościelnicka
xilinx: Add FDRSE_1, FDCPE_1.
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2021-01-26
whitequark
Merge pull request #2563 from whitequark/cxxrtl-msvc
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2021-01-26
whitequark
Merge pull request #2544 from modwizcode/fix-clock
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2021-01-26
whitequark
flatten: clarify confusing error message.
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2021-01-26
whitequark
cxxrtl: do not use `->template` for non-dependent names.
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2021-01-26
Dan Ravensloft
scc: Add -specify option to find loops in boxes
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2021-01-26
Yosys Bot
Bump version
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2021-01-25
whitequark
Merge pull request #2549 from pgadfort/support-multiple...
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2021-01-25
whitequark
Merge pull request #2550 from zachjs/macro-arg-spaces
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2021-01-25
Yosys Bot
Bump version
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2021-01-24
Claire Xen
Merge pull request #2558 from YosysHQ/dave/chandle-dpi
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2021-01-23
David Shah
dpi: Support for chandle type
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2021-01-22
Yosys Bot
Bump version
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2021-01-21
Miodrag Milanović
Merge pull request #2553 from zachjs/rand-const-modifiers
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2021-01-21
Zachary Snow
Allow combination of rand and const modifiers
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2021-01-21
Yosys Bot
Bump version
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2021-01-20
Claire Xen
Merge pull request #2552 from YosysHQ/claire/yosyshq
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2021-01-20
Claire Xenia...
Switch verific bindings from Symbiotic EDA flavored...
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2021-01-20
Miodrag Milanović
Merge pull request #2536 from TobiasFaller/master
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2021-01-20
Miodrag Milanović
Merge pull request #2551 from zachjs/wire-logic
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2021-01-20
Zachary Snow
sv: fix support wire and var data type modifiers
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2021-01-20
Zachary Snow
verilog: allow spaces in macro arguments
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2021-01-19
Yosys Bot
Bump version
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2021-01-18
Peter Gadfort
adding support for passing multiple liberty files to abc
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2021-01-18
whitequark
Merge pull request #2547 from zachjs/plugin-so-dsym
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2021-01-18
whitequark
Merge pull request #2312 from antmicro/typedef-inout
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2021-01-18
Zachary Snow
Add plugin.so.dSYM to .gitignore
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2021-01-18
Kamil Rakoczy
Add typedef input/output test
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2021-01-18
Kamil Rakoczy
Fix input/output attributes when resolving typedef...
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2021-01-18
Lukasz Dalek
Parse package user type in module port list
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2021-01-15
Iris Johnson
Improves the previous commit with a more complete cover...
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2021-01-15
Yosys Bot
Bump version
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2021-01-14
Iris Johnson
Handle sliced bits as clock inputs (fixes #2542)
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2021-01-14
Marcelina Kościelnicka
opt_share: Fix X and CO signal width for shifted $alu...
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2021-01-14
Yosys Bot
Bump version
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2021-01-13
Claire Xen
Merge pull request #2537 from pepijndevos/spice
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2021-01-13
Pepijn de Vos
add buffer option to spice backend
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2021-01-12
Tobias Faller
Fixed missing goto statement in passes/techmap/abc.cc
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2021-01-05
Yosys Bot
Bump version
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2021-01-04
whitequark
Merge pull request #2522 from tomverbeure/simlib_typos2
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