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riscv-isa-sim.git
2016-12-12
Tim Newsome
Reuse the ebreak constants in encoding.h.
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2016-12-01
Andy Wright
Added comments about the modified Duff's Device in...
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2016-11-14
Andrew Waterman
Fix 32-bit host portability bug
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2016-11-12
Ben Gamari
Ensure that g++ knows it is building a PCH (#75)
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2016-11-10
Andrew Waterman
AMOs should always return store faults, not load faults
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2016-10-31
Tim Newsome
Make reading/writing fpu regs work.
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2016-10-31
Tim Newsome
Minor code cleanup.
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2016-10-31
Tim Newsome
Check for exception after register write.
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2016-10-28
Tim Newsome
Check for exception after reading a register.
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2016-10-28
Tim Newsome
Fix error message.
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2016-10-25
Tim Newsome
Increase gdb receive buffer.
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2016-10-10
Andrew Waterman
Don't force load trigger timing to After
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2016-10-07
Tim Newsome
Don't die when gdb thinks XLEN is 64 but it's 32.
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2016-09-30
Tim Newsome
Return an error to gdb when memory reads fail. (#71)
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2016-09-29
Tim Newsome
Update trigger behavior. (#70)
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2016-09-13
Scott Beamer
restore clang support by fixing printf identifiers
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2016-09-10
Andrew Waterman
allow MAFDC bits in MISA to be modified
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2016-09-06
Tim Newsome
Remove generic debug tests. (#65)
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2016-09-02
Andrew Waterman
Merge pull request #62 from riscv/trigger
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2016-09-02
Tim Newsome
Merge branch 'master' into trigger
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2016-09-02
Tim Newsome
Rebuild debug ROM because CSR encoding changed.
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2016-09-02
Tim Newsome
Support triggers on TLB misses.
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2016-09-01
Tim Newsome
Theoretically support trigger timing.
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2016-08-31
Tim Newsome
Rename tdata[0-2] to tdata[1-3].
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2016-08-31
Tim Newsome
Save/restore tselect. Set dmode.
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2016-08-29
Tim Newsome
Fix indent.
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2016-08-29
Tim Newsome
Rename tdata0--tdata2 to tdata1--tdata3.
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2016-08-27
Andrew Waterman
Add (degenerate) performance counter facility
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2016-08-26
Andrew Waterman
Allow reads from tdrdata registers
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2016-08-26
Andrew Waterman
partially update spike to newer debug spec
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2016-08-26
Andrew Waterman
Fix spike interactive (-d) mode
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2016-08-23
Andrew Waterman
remove HWBPCOUNT field of DCSR
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2016-08-22
Tim Newsome
Implement address and data triggers.
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2016-08-17
Andrew Waterman
Allow mstatus.MPP to store bad values; instead, validat...
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2016-08-16
Colin Schmidt
remove old rvc directory (#61)
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2016-07-28
Tim Newsome
Add support for virtual priv register. (#59)
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2016-07-22
Andrew Waterman
Set U bit in misa register
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2016-07-19
Tim Newsome
Make address translation work in 32-bit. (#58)
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2016-07-13
Tim Newsome
Fix single step over csrw instructions. (#57)
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2016-07-12
Andrew Waterman
Don't treat RVC NOP as illegal instruction
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2016-07-12
Andrew Waterman
Fix page table walker not respecting valid bit
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2016-07-06
Andrew Waterman
Update to new PTE format
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2016-07-01
Tim Newsome
Remove debug printf that was cluttering up output.
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2016-06-29
Andrew Waterman
Disassemble RVC instructions based on XLEN
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2016-06-28
Tim Newsome
Make gdbserver code work with small Debug RAM.
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2016-06-28
Tim Newsome
Support debugging 32-bit spike instances.
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2016-06-23
Andrew Waterman
Parameterize debug ROM contents on XLEN
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2016-06-23
Andrew Waterman
Remove fence.i from debug ROM
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2016-06-23
Andrew Waterman
Don't use I$ in debug mode
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2016-06-23
Andrew Waterman
Remove legacy HTIF; implement HTIF directly
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2016-06-23
Andrew Waterman
Fix paddr_bits computation prior to VM setup
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2016-06-18
Andrew Waterman
Merge sasid into sptbr
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2016-06-09
Andrew Waterman
Trap on tdrdata registers when tdrselect[XLEN-1]=0
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2016-06-09
Jonathan Neuschäfer
make check: Fail if the tests failed
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2016-06-09
Tim Newsome
Fix 2 bugs in Debug ROM: (#52)
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2016-06-09
Andrew Waterman
Add degenerate HW breakpoint implementation
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2016-06-03
Tim Newsome
Keep DCSR_XDEBUGVER unsigned.
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2016-06-03
neuschaefer
Minor usability improvements (#48)
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2016-06-03
Tim Newsome
DCSR cause was moved, bug debug ROM wasn't updated
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2016-06-02
Tim Newsome
Fix 'make check' when run from build directory.
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2016-06-01
Andrew Waterman
Fix build when not building inside root directory
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2016-06-01
Andrew Waterman
Add gitignore
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2016-06-01
Tim Newsome
Move sethaltnot and cleardebint.
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2016-05-24
Tim Newsome
New encoding.h for new CSR addresses.
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2016-05-24
Tim Newsome
Move cleardebint, per spec.
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2016-05-23
Tim Newsome
Use .word for mret, for now.
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2016-05-23
Tim Newsome
Change DCSR bits to match spec.
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2016-05-23
Tim Newsome
Kill spike as soon as the test is done with it.
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2016-05-23
Tim Newsome
Link standalone programs at 0x80010000.
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2016-05-23
Tim Newsome
Turn off debugging.
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2016-05-23
Tim Newsome
Tell gdb we can handle large packets.
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2016-05-23
Tim Newsome
Fix writing odd numbers of bytes to odd addresses.
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2016-05-23
Tim Newsome
Exceptions in Debug Mode don't update any regs.
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2016-05-23
Tim Newsome
Ignore MPRV in Debug Mode.
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2016-05-23
Tim Newsome
Write test for downloading a mostly random program
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2016-05-23
Tim Newsome
Remove already-implemented TODO.
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2016-05-23
Tim Newsome
Move debug rom link map to the right place.
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2016-05-23
Tim Newsome
Remove obsolete TODO.
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2016-05-23
Tim Newsome
Implement ebreak[mhsu].
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2016-05-23
Tim Newsome
Remove dependency on include file in my homedir.
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2016-05-23
Tim Newsome
Force gdb to not print entry values.
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2016-05-23
Tim Newsome
mprv test now breaks like it's supposed to.
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2016-05-23
Tim Newsome
Deal with escapes that gdb sends in binary data.
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2016-05-23
Tim Newsome
Make -H halt the core right out of reset.
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2016-05-23
Tim Newsome
Halt when gdb user hits ^C.
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2016-05-23
Tim Newsome
Make sure to fence.i after setting/clearing a swbp
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2016-05-23
Tim Newsome
Implemented register writes.
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2016-05-23
Tim Newsome
Fix reading CSRs.
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2016-05-23
Tim Newsome
Single step appears to work.
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2016-05-23
Tim Newsome
Software breakpoints sort of work.
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2016-05-23
Tim Newsome
Use fence.i in Debug ROM.
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2016-05-23
Tim Newsome
Fix off-by-two in general read registers.
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2016-05-23
Tim Newsome
Walk page tables to translate addresses.
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2016-05-23
Tim Newsome
Turn operation into a queue,
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2016-05-23
Tim Newsome
Remove unused code.
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2016-05-23
Tim Newsome
Save/restore mstatus, too.
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2016-05-23
Tim Newsome
Ignore more files.
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2016-05-23
Tim Newsome
Properly read s0/s1.
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2016-05-23
Tim Newsome
Add dret.
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2016-05-23
Tim Newsome
Implement memory writes.
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