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microwatt.git
2019-09-09 Benjamin HerrenschmidtAdd simulated UART design commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #31 from antonblanchard/no-second... commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #30 from antonblanchard/writeback... commit | commitdiff | tree
2019-09-09 Anton BlanchardMore second write port removal commit | commitdiff | tree
2019-09-09 Anton BlanchardAdd some assertions to writeback commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #29 from antonblanchard/no-second... commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #28 from antonblanchard/loadstore... commit | commitdiff | tree
2019-09-09 Anton BlanchardRemove second write port commit | commitdiff | tree
2019-09-09 Anton BlanchardRemove some more loadstore debug commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #27 from antonblanchard/fix-cr commit | commitdiff | tree
2019-09-09 Anton BlanchardFix issues with CR rework commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #26 from antonblanchard/silence... commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #25 from antonblanchard/register_fil... commit | commitdiff | tree
2019-09-09 Anton BlanchardMerge pull request #24 from antonblanchard/cr_file_cleanup commit | commitdiff | tree
2019-09-09 Anton BlanchardSilence some loadstore related debug commit | commitdiff | tree
2019-09-09 Anton BlanchardClean up register read debug output commit | commitdiff | tree
2019-09-09 Anton BlanchardRework CR file and add forwarding commit | commitdiff | tree
2019-09-08 Anton BlanchardMerge pull request #19 from antonblanchard/cmod-a7 commit | commitdiff | tree
2019-09-08 Anton BlanchardCmod A7-35 support commit | commitdiff | tree
2019-09-08 Anton BlanchardMerge pull request #20 from antonblanchard/reset-rework2 commit | commitdiff | tree
2019-09-08 Anton BlanchardMerge pull request #22 from antonblanchard/store-fix commit | commitdiff | tree
2019-09-08 Anton BlanchardStores need to wait for wishbone write ack commit | commitdiff | tree
2019-09-08 Anton BlanchardMerge pull request #21 from antonblanchard/xdc-update commit | commitdiff | tree
2019-09-07 Anton BlanchardAdd CONFIG_VOLTAGE and CFGBVS entries commit | commitdiff | tree
2019-09-07 Anton BlanchardRework SOC reset commit | commitdiff | tree
2019-09-07 Anton BlanchardRename a few reset signals commit | commitdiff | tree
2019-09-06 Anton BlanchardMerge pull request #18 from mikey/verific commit | commitdiff | tree
2019-09-06 Michael NeulingFix verific script with new VHDL files commit | commitdiff | tree
2019-09-06 Anton BlanchardMerge pull request #17 from antonblanchard/writeback... commit | commitdiff | tree
2019-09-05 Anton BlanchardUse a better input signal in writeback commit | commitdiff | tree
2019-09-03 Anton BlanchardMerge pull request #16 from antonblanchard/decode2_rework2 commit | commitdiff | tree
2019-09-03 Anton BlanchardRework decode2 commit | commitdiff | tree
2019-08-31 Anton BlanchardMerge pull request #13 from mikey/dynamic-ranges commit | commitdiff | tree
2019-08-30 Michael NeulingRemove dynamic ranges from code commit | commitdiff | tree
2019-08-29 Anton BlanchardMerge pull request #10 from antonblanchard/arty-fix commit | commitdiff | tree
2019-08-29 Anton BlanchardArty A7 reset pin is C2 commit | commitdiff | tree
2019-08-29 Anton BlanchardMerge pull request #7 from riktw/fusesoc_arty_a7 commit | commitdiff | tree
2019-08-29 Anton BlanchardMerge pull request #9 from antonblanchard/travis-fix commit | commitdiff | tree
2019-08-29 Anton BlanchardA few Travis CI fixes commit | commitdiff | tree
2019-08-29 riktwAdded support for building for Arty A7 boards commit | commitdiff | tree
2019-08-28 Anton BlanchardMerge pull request #5 from antonblanchard/travis-test commit | commitdiff | tree
2019-08-28 Anton BlanchardAdd an initial travis.yml commit | commitdiff | tree
2019-08-28 Anton BlanchardAdd srd and srw commit | commitdiff | tree
2019-08-28 Anton BlanchardAdd sim only divw commit | commitdiff | tree
2019-08-27 Anton BlanchardFix ghdl build error with pp_soc_memory commit | commitdiff | tree
2019-08-27 Anton Blanchardmicropython only requires 512kB of BRAM commit | commitdiff | tree
2019-08-27 Anton BlanchardMerge pull request #6 from mikey/gif commit | commitdiff | tree
2019-08-27 Anton BlanchardAdd -Wall to CFLAGS commit | commitdiff | tree
2019-08-27 Michael NeulingAdd pretty gif demo of MicroPython on Microwatt to... commit | commitdiff | tree
2019-08-26 Anton BlanchardAdd missing argument to fprintf warning commit | commitdiff | tree
2019-08-26 Anton BlanchardAdd some initial FPGA synthesis instructions commit | commitdiff | tree
2019-08-26 Anton BlanchardRebuild hello world assuming a 50MHz clock commit | commitdiff | tree
2019-08-26 Anton BlanchardMerge pull request #3 from olofk/plle2 commit | commitdiff | tree
2019-08-26 Olof KindgrenAdd and use plle2 primitive for nexys boards commit | commitdiff | tree
2019-08-26 Anton BlanchardMerge pull request #4 from sharkcz/build commit | commitdiff | tree
2019-08-24 Dan Horákdon't cross compile when on Power commit | commitdiff | tree
2019-08-23 Anton BlanchardAdd a simple hello_world example that also echos input commit | commitdiff | tree
2019-08-23 Anton BlanchardMerge pull request #2 from olofk/fusesoc_nexys_a7 commit | commitdiff | tree
2019-08-23 Olof KindgrenAdded synthesis target commit | commitdiff | tree
2019-08-23 Olof KindgrenAdd Nexys Video support commit | commitdiff | tree
2019-08-23 Olof KindgrenAdd FuseSoC core description file with Nexys A7 support commit | commitdiff | tree
2019-08-23 Olof KindgrenAdd constraint file for Nexys A7 commit | commitdiff | tree
2019-08-23 Olof KindgrenExpose ram init file and memory size through toplevel commit | commitdiff | tree
2019-08-23 Olof KindgrenAdd dummy clock generator commit | commitdiff | tree
2019-08-23 Anton BlanchardAdd a few more FPGA related files commit | commitdiff | tree
2019-08-22 Anton BlanchardInitial import of microwatt commit | commitdiff | tree