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riscv-isa-sim.git
2014-02-11
Andrew Waterman
Revert to old AUIPC definition
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2014-02-07
Andrew Waterman
Clear EVEC LSBs, which kindly prevents a segfault
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2014-02-06
Andrew Waterman
Fix disassembly of JAL
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2014-02-06
Yunsup Lee
commit missing definitions for uarch counters
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2014-02-04
Quan Nguyen
Move half precision instructions, add vfmsv, vfmvv
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2014-02-01
Andrew Waterman
Fix linking on Darwin
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2014-01-29
Christopher...
Disasm now translates xor x0,x0,x0 as a machine-generat...
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2014-01-28
Andrew Waterman
Force extension loaders to be linked in
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2014-01-27
Andrew Waterman
Enable runtime loading of dynamic library with --extlib
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2014-01-27
Andrew Waterman
Prefer libraries located in current directory
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2014-01-27
Andrew Waterman
Eliminate hwacha <-> riscv circular dependence
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2014-01-27
Andrew Waterman
Link subproject dynamic libraries correctly
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2014-01-26
Andrew Waterman
Merge softfloat_riscv into softfloat
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2014-01-24
Andrew Waterman
Require libdl for dynamic linking at runtime
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2014-01-24
Andrew Waterman
Disassemble amoxor
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2014-01-24
Andrew Waterman
Build and use shared libraries only
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2014-01-24
Andrew Waterman
Build and use shared libraries
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2014-01-24
Andrew Waterman
Handle CSR permissions correctly
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2014-01-22
Andrew Waterman
Use auto-generated trap cause numbers
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-16
Andrew Waterman
Initialize tohost and fromhost to zero
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-12-17
Andrew Waterman
Speed things up quite a bit
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2013-12-09
Andrew Waterman
New RDCYCLE encoding
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2013-11-30
Quan Nguyen
Remove debug printf in vsetprec
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2013-11-30
Quan Nguyen
Add vsetprec instruction prototype
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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2013-11-25
Quan Nguyen
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-11-21
Yunsup Lee
fix slli/slliw encoding bug
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2013-11-06
Yunsup Lee
add accelerator disabled cause
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2013-11-06
Yunsup Lee
correctly trap when SR_EA is disabled
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2013-11-05
Albert Ou
Fix declaration of half-precision instructions
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2013-11-05
Albert Ou
Re-add Hwacha header file
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2013-11-05
Albert Ou
Implement "half-baked" half-precision instruction subse...
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-29
Yunsup Lee
include stdexcept
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2013-10-29
Andrew Waterman
Pass target machine's return code back to OS
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2013-10-28
Quan Nguyen
Add missing fcvt opcodes through riscv-opcodes
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2013-10-22
Yunsup Lee
clarify vxcptsave/vxctkill semantics
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2013-10-19
Yunsup Lee
implement vxcptsave/vxcptrestore
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2013-10-19
Yunsup Lee
clean up SR_EA, the enable accelerator bit in status reg
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2013-10-19
Yunsup Lee
more hwacha supervisor stuff
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-10-18
Yunsup Lee
can't execute frsr/fssr on ut
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2013-10-18
Yunsup Lee
or into control thread's fp exceptions
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2013-10-18
Quan Nguyen
Add empty opcode header files for half-precision
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2013-10-18
Yunsup Lee
catch trap_illegal_instruction in hwacha
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2013-10-18
Yunsup Lee
add hwacha exception support
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2013-10-18
Yunsup Lee
fix custom-1 rocc encoding
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2013-10-16
Yunsup Lee
fix maxvl calc logic
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2013-10-16
Yunsup Lee
use reset virtual method
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2013-10-16
Yunsup Lee
use uint32_t for vl
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2013-10-16
Yunsup Lee
fix missing null check when there's no extension
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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2013-10-15
Stephen Twigg
Propogate the reset call to the extensions as well...
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2013-10-15
Stephen Twigg
Fix bug where xs2 was not being properly respected.
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2013-10-10
Yunsup Lee
commit configure script; new configure option --enable...
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2013-09-27
Christopher...
Added commit logging (--enable-commitlog). Also fixed...
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2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
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2013-09-27
Andrew Waterman
Bye, CB
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2013-09-23
Scott Beamer
fixes compile bug for not being able to find std::logic...
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2013-09-23
Andrew Waterman
Fix Scott's deadlock
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2013-09-22
Stephen Twigg
Adjust rocc_inst_t to properly extract fields due to...
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2013-09-21
Andrew Waterman
Update ISA encoding and AUIPC semantics
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2013-09-15
Andrew Waterman
Add helper disassembly program
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2013-09-15
Andrew Waterman
ISA changes
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2013-09-11
Andrew Waterman
Add AMOXOR
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2013-09-11
Andrew Waterman
Implement zany immediates
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2013-09-10
Andrew Waterman
Don't tick HTIF as often
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2013-09-10
Andrew Waterman
Add rd field to JAL; drop J
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2013-08-18
Andrew Waterman
Renumber PCRs
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2013-08-13
Andrew Waterman
Add test program for dummy rocc
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2013-08-13
Andrew Waterman
Implement RoCC and add a dummy RoCC
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2013-08-12
Andrew Waterman
Instructions are no longer member functions
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2013-08-08
Andrew Waterman
Ignore JALR's effective address LSB
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2013-08-08
Andrew Waterman
Disentangle some header files
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2013-08-08
Andrew Waterman
Rename MTFSR/MFFSR to FSSR/FRSR
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2013-08-08
Andrew Waterman
Swap J and JALR encoding
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2013-08-01
Quan Nguyen
Fix eret (again)
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2013-07-31
Andrew Waterman
Fix dumb ERET bug
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2013-07-29
Andrew Waterman
Don't flush TLB on PTBR writes (only FATC)
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2013-07-27
Andrew Waterman
New supervisor mode
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2013-07-27
Andrew Waterman
Remove more vector stuff
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2013-07-27
Andrew Waterman
Rename MFTX/MXTF to FMV
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2013-07-26
Andrew Waterman
Rip out Hwacha for now
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2013-07-26
Andrew Waterman
Rip out RVC for now
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2013-07-26
Andrew Waterman
Generate instruction decoder dynamically
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2013-07-25
Andrew Waterman
Remove JALR static hints
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2013-07-23
Andrew Waterman
Kill spike when xspike is SIGINTed
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2013-07-22
Andrew Waterman
Don't use stdout for debugging
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2013-07-22
Andrew Waterman
Add xspike program
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2013-07-20
Andrew Waterman
Use calloc to allocate target memory
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2013-07-13
Andrew Waterman
Eliminate infinite loop in debug mode
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2013-07-13
Andrew Waterman
Exit cleanly from debug console
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2013-07-13
Andrew Waterman
Favor procs.size() over num_cores()
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2013-07-13
Andrew Waterman
Fix SR_U64 bit being ignored
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2013-06-03
Andrew Waterman
make spike.o correctly depend on dispatch.h
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2013-06-03
Andrew Waterman
use coreutils `seq' instead of hacky `range'
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2013-05-15
Yunsup Lee
change riscv-isa-run to spike in documentation
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2013-05-15
Yunsup Lee
fix make issue
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