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gem5.git
2015-03-07
Steve Reinhardt
stats: update eio stats
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2015-03-02
Andreas Hansson
stats: Update stats to reflect cache and interconnect...
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2015-03-02
Andreas Hansson
mem: Unify all cache DPRINTF address formatting
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2015-03-02
Andreas Hansson
mem: Fix cache MSHR conflict determination
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2015-03-02
Andreas Hansson
mem: Add byte mask to Packet::checkFunctional
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2015-03-02
Stephan Diestelhorst
mem: Add option to force in-order insertion in PacketQueue
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2015-03-02
Marco Balboni
mem: Downstream components consumes new crossbar delays
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2015-03-02
Andreas Hansson
mem: Move crossbar default latencies to subclasses
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2015-03-02
Marco Balboni
mem: Add crossbar latencies
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2015-03-02
Andreas Sandberg
dev, arm: Clean up PL011 and rewrite interrupt handling
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2015-03-02
Andreas Hansson
arm: Share a port for the two table walker objects
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2015-03-02
Giacomo Gabrielli
arm: Remove unnecessary dependencies between AArch64...
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2015-03-02
Rekai
cpu: o3 register renaming request handling improved
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2015-03-02
Andreas Hansson
mem: Tidy up the cache debug messages
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2015-03-02
Andreas Hansson
mem: Split port retry for all different packet classes
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2015-03-02
Ali Jafri
mem: Fix prefetchSquash + memInhibitAsserted bug
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2015-03-02
Stephan Diestelhorst
cpu: Add a PC-value to the traffic generator requests
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2015-03-02
Andreas Hansson
tests: Run regression timeout as foreground
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2015-03-02
Andreas Sandberg
arm: Don't truncate 16-bit ASIDs to 8 bits
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2015-03-02
Andreas Sandberg
arm: Correctly access the stack pointer in GDB
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2015-03-02
Andreas Sandberg
arm: Fix broken page table permissions checks in remote GDB
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2015-02-26
Jason Power
Ruby: Update backing store option to propagate through...
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2015-02-16
Andreas Hansson
config: Add memcheck stress test
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2015-02-16
Andreas Hansson
cpu: TrafficGen sinks snoops without complaining
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2015-02-16
Stephan Diestelhorst
mem: Fix initial value problem with MemChecker
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2015-02-16
Andreas Hansson
dev: Fix undefined behaviuor in i8254xGBe
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2015-02-16
Andreas Sandberg
arm: Wire up the GIC with the platform in the base...
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2015-02-16
Andreas Hansson
mem: mmap the backing store with MAP_NORESERVE
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2015-02-16
Andreas Hansson
mem: Use the range cache for lookup as well as access
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2015-02-16
Andreas Hansson
arch: Make readMiscRegNoEffect const throughout
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2015-01-16
Curtis Dunham
config: add --root-device machine parameter
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2015-02-16
Andreas Sandberg
arm: Merge ISA files with pseudo instructions
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2015-02-16
Ali Saidi
cpu: add support for outputing a protobuf formatted...
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2015-02-11
Marco Balboni
mem: Clarification of packet crossbar timings
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2015-02-11
Marco Balboni
mem: Clarify usage of latency in the cache
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2015-02-11
Andreas Sandberg
style: Fix broken m5format command
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2015-02-11
Andreas Sandberg
style: Fix incorrect style checker option name
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2015-02-11
Andreas Hansson
config: Revamp memtest to allow testers on any level
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2015-02-11
Andreas Hansson
stats: Bump the MemTest regression stats
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2015-02-11
Andreas Hansson
cpu: Tidy up the MemTest and make false sharing more...
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2015-02-11
Andreas Sandberg
sim: Move the BaseTLB to src/arch/generic/
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2015-02-11
Andreas Sandberg
base: Add compiler macros to add deprecation warnings
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2015-02-11
Andreas Hansson
base: Do not dereference NULL in CompoundFlag creation
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2015-02-11
Andreas Sandberg
dev: Remove unused system pointer in the Platform base...
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2015-02-07
Alexandru Dutu
cpu: Idle CPU status logic revised
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2015-02-06
Steve Reinhardt
config: rename 'file' var
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2015-02-06
Steve Reinhardt
config: make M5_PATH a real search path
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2015-02-03
Andreas Hansson
mem: Clarify express snoop behaviour
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2015-02-03
Andreas Hansson
mem: Clarify cache behaviour for pending dirty responses
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2015-02-03
Curtis Dunham
base: add an accessor and operators ==,!= to address...
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2015-02-03
Andreas Hansson
config: Add XOR hashing to the DRAM channel interleaving
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2015-02-03
Andreas Hansson
base: Add XOR-based hashed address interleaving
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2015-02-03
Andreas Hansson
config: Adjust DRAM channel interleaving defaults
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2015-02-03
Andreas Sandberg
style: Update the style checker to handle new include...
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2015-02-03
Andreas Sandberg
sim: Remove test for non-NULL this in Event
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2015-02-03
Andreas Sandberg
dev: Correctly clear interrupts in VirtIO PCI
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2015-02-03
Andreas Hansson
scons: Avoid implicit command dependencies
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2014-12-19
Curtis Dunham
sim: prioritize async events; prevent starvation
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2015-02-03
Andreas Hansson
cpu: Ensure timing CPU sinks response before sending...
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2015-02-03
Geoffrey Blake
config: Fix typo in Float param
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2015-01-30
Malek Musleh
config: arm: fix os_flags
stable_2015_04_15
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2015-01-25
Ali Saidi
arm: always set the IsFirstMicroop flag
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2015-01-25
Ali Saidi
sim: Clean up InstRecord
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2015-01-25
Ali Saidi
cpu: Remove all notion that we know when the cpu is...
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2015-01-25
Ali Saidi
cpu: Put all CPU instruction tracers in a single file
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2015-01-25
Ali Saidi
cpu: remove legion tracer
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2014-12-23
Curtis Dunham
sim: fix reference counting of PythonEvent
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2015-01-22
Andreas Hansson
mem: Remove unused Packet src and dest fields
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2015-01-22
Andreas Hansson
mem: Remove Packet source from ForwardResponseRecord
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2015-01-22
Andreas Hansson
mem: Remove unused RequestState in the bridge
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2015-01-22
Andreas Hansson
mem: Always use SenderState for response routing in...
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2015-01-22
Andreas Hansson
mem: Make the XBar responsible for tracking response...
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2015-01-22
Andreas Hansson
stats: Update stats to reflect x86 table walker changes
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2015-01-22
Andreas Hansson
x86: Delay X86 table walk on receiving walker response
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2015-01-22
Andreas Hansson
mem: Clean up Request initialisation
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2015-01-20
Malek Musleh
config, ruby: connect dma to network
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2015-01-20
Nikos Nikoleris
cpu: commit probe notification on every microop or...
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2015-01-20
Andreas Hansson
scons: Do not build the InOrderCPU
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2015-01-20
Andreas Hansson
tests: Remove deprecated InOrderCPU tests
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2015-01-20
Andreas Hansson
mem: Fix bug in cache request retry mechanism
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2015-01-20
Andreas Hansson
cpu: Fix retry bug in MinorCPU LSQ
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2015-01-20
Andreas Hansson
mem: Move DRAM interleaving check to init
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2015-01-11
Nilay Vaish
stats: changes due to recent changesets.
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2015-01-10
Emilio Castillo
x86 : fxsave and fxrestore missing template code
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2015-01-10
Nikos Nikoleris
cpu: fix RetiredStores probe point
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2015-01-06
cdirik
dev: prevent intel 8254 timer counter events firing...
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2015-01-07
Gabe Black
test: Add a unittest for the BitUnion types.
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2015-01-07
Gabe Black
base: Fix assigning between identical bitfields.
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2015-01-07
Gabe Black
stats: x86: Update stats for the CPUID change.
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2015-01-07
Gabe Black
x86: Enable three bits in the FamilyModelStepping ECX...
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2015-01-07
Gabe Black
cpuid, x86: Revert "Enabling more features in CPUid"
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2015-01-04
Nilay Vaish
stats: changes due to recent changesets.
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2015-01-03
Anthony Gutierrez
arm: fix build_drive_system when not using default...
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2015-01-03
Andrew Lukefahr
minor: fixed LSQ MasterPortID
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2015-01-03
mike upton
arm: Add unlinkat syscall implementation
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2015-01-03
Maxime Martinasso
x86: implements the simd128 ADDSUBPD instruction
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2015-01-03
Cagdas Dirik
dev: prevent RTC events firing before startup
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2015-01-03
Nilay Vaish
configs: ruby: removes bug introduced by 05b5a6cf3521
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2014-12-27
Joel Hestness
syscall_emul: Return correct writev value
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2014-12-23
Andreas Hansson
stats: Bump stats for decoder, TLB, prefetcher and...
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