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yosys.git
2014-03-06
Clifford Wolf
Fixed gcc compiler warning
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2014-03-06
Clifford Wolf
Fixed undef handling in opt_reduce
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2014-03-06
Clifford Wolf
Fixes for improved techmap of shifts with large B inputs
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2014-03-06
Clifford Wolf
Fixed use of frozen literals in SatGen
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2014-03-06
Clifford Wolf
Strictly zero-extend unsigned A-inputs of shift operati...
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2014-03-06
Clifford Wolf
Added techmap -max_iter option
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2014-03-06
Clifford Wolf
Improved techmap of shift with wide B inputs
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2014-03-06
Clifford Wolf
Strictly zero-extend unsigned A-inputs of shift operations
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2014-03-05
Clifford Wolf
Switched to EZMINISAT_SIMPSOLVER as default SAT solver
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2014-03-05
Clifford Wolf
Include id2ast pointers when dumping AST
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2014-03-05
Clifford Wolf
Fixed merging of compatible wire decls in AST frontend
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2014-03-05
Clifford Wolf
Bugfix in recursive AST simplification
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2014-03-03
Clifford Wolf
fixed freduce for Minisat::SimpSolver: use frozen_literal()
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2014-03-03
Clifford Wolf
ezSAT: Added frozen_literal() API
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2014-03-03
Clifford Wolf
ezSAT: Fixed handling of eliminated Literals, added...
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2014-03-01
Clifford Wolf
Added ezSAT::eliminated API to help the SAT solver...
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2014-03-01
Clifford Wolf
ezSAT bugfix: don't call virtual methods in base class...
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2014-03-01
Clifford Wolf
Removed ezSAT::assumed() API
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2014-03-01
Clifford Wolf
Removed ezSAT built-in brute-froce solver
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2014-03-01
Clifford Wolf
Fixed vhdl2verilog temp dir name
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2014-03-01
Clifford Wolf
Fixed vhdl2verilog help message
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2014-02-27
Clifford Wolf
Fixed const folding of $bu0 cells
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2014-02-26
Clifford Wolf
Fixed bit-extending in $mux argument (use $bu0 instead...
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2014-02-26
Clifford Wolf
Added support for $bu0 to SatGen
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2014-02-24
Clifford Wolf
Don't blow up constants unneccessarily in Verilog frontend
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2014-02-23
Clifford Wolf
Added support for Minisat::SimpSolver + ezSAT frezze...
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2014-02-23
Clifford Wolf
Fixed small memory leak in Pass::call()
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2014-02-22
Clifford Wolf
Fixed bug in generation of undefs for $memwr MUXes
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2014-02-22
Clifford Wolf
Fixed bug (typo) in passes/opt/opt_const.cc
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2014-02-22
Clifford Wolf
Added $lut support to blif backend (by user eddiehung...
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2014-02-22
Clifford Wolf
Added ezMiniSat EZMINISAT_INCREMENTAL compile-time...
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2014-02-22
Clifford Wolf
Made MiniSat solver backend configurable in ezminisat.h
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2014-02-21
Clifford Wolf
Added workaround for vhdl-style edge triggers from...
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2014-02-21
Clifford Wolf
Added vhdl2verilog
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2014-02-21
Clifford Wolf
Progress in presentation
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2014-02-21
Clifford Wolf
Better handling of nameDef and nameRef in edif backend
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2014-02-21
Clifford Wolf
Fixed instantiating multi-bit ports in edif backend
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2014-02-21
Clifford Wolf
Use private namespace in mem_simple_4x1_map
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2014-02-21
Clifford Wolf
Added tests/techmap/mem_simple_4x1
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2014-02-21
Clifford Wolf
Renamed "write_blif -subckt" to "write_blif -icells...
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2014-02-21
Clifford Wolf
Progress in presentation
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2014-02-20
Clifford Wolf
Progress in presentation
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2014-02-20
Clifford Wolf
Added _TECHMAP_REPLACE_ feature to techmap
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2014-02-20
Clifford Wolf
Added "extract -ignore_parameters" and "extract -ignore...
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2014-02-20
Clifford Wolf
Added "extract -map %<design_name>"
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2014-02-20
Clifford Wolf
Added "design -push" and "design -pop"
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2014-02-20
Clifford Wolf
Progress in presentation
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2014-02-20
Clifford Wolf
Added connwrappers command
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2014-02-20
Clifford Wolf
Cleanups in handling of read_verilog -defer and -icells
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2014-02-20
Clifford Wolf
Progress in presentation
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2014-02-19
Clifford Wolf
Added vcd2txt.pl and txt2tikztiming.py (tests/tools...
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2014-02-18
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-18
Clifford Wolf
Progress in presentation
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2014-02-18
Clifford Wolf
Added techmap support for _TECHMAP_CONNMAP_*_
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2014-02-18
Clifford Wolf
Added "sat -dump_cnf"
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2014-02-18
Clifford Wolf
Coding style corrections in SatHelper::dump_model_to_vcd()
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2014-02-18
Clifford Wolf
Improved non-verbose ezSAT::printDIMACS() format
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2014-02-18
Clifford Wolf
Added "sat -initsteps"
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2014-02-17
Clifford Wolf
Added Verilog support for "`default_nettype none"
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2014-02-17
Clifford Wolf
Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"...
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2014-02-17
Andrew Zonenberg
Added "-dump_fail_to_vcd" argument to SAT solver
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2014-02-17
Clifford Wolf
Progress in presentation
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2014-02-17
Clifford Wolf
Better preserve wires when flattening (in comparison...
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Added some additional checks to techmap
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2014-02-16
Clifford Wolf
Added CONSTMSK and CONSTVAL feature to techmap
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2014-02-16
Clifford Wolf
Fixed handling of "keep" attribute on wires in opt_clean
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2014-02-16
Clifford Wolf
Added a warning note about error reporting to read_veri...
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Fixed use of selection in splitnets command
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2014-02-16
Clifford Wolf
Added recursion support to techmap
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Improved support for constant functions
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2014-02-15
Clifford Wolf
Now we are in Yoys 0.2.0+ development
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2014-02-15
Clifford Wolf
Tagging Yoys 0.2.0
yosys-0.2.0
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2014-02-15
Clifford Wolf
Added != support for relational select pattern
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2014-02-15
Clifford Wolf
Added iopadmap -bits
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2014-02-15
Clifford Wolf
Added ff and latch support to read_liberty
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2014-02-15
Clifford Wolf
Bugfix in expression parser of read_liberty
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2014-02-15
Clifford Wolf
Fixed dfflibmap for cell libraries with no set-reset-ff
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2014-02-15
Clifford Wolf
Correctly convert constants to RTLIL (fixed undef handling)
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2014-02-15
Clifford Wolf
Added frontend (-f) option to autotest.sh
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2014-02-15
Clifford Wolf
Fixed opt_const handling of double invert with non...
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2014-02-15
Clifford Wolf
Added liberty frontend
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2014-02-14
Clifford Wolf
Be more conservative with new const-function code
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2014-02-14
Clifford Wolf
Added support for FOR loops in function calls in parameters
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2014-02-14
Clifford Wolf
Created basic support for function calls in parameter...
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2014-02-14
Clifford Wolf
Added abc -keepff option
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2014-02-13
Clifford Wolf
updated default ABC command strings
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2014-02-13
Clifford Wolf
Updated ABC
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2014-02-13
Clifford Wolf
Implemented read_verilog -defer
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2014-02-13
Clifford Wolf
Removed double blanks in ABC default command sequences
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2014-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-13
Clifford Wolf
Updated ABC and some related changes
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2014-02-12
Clifford Wolf
Merge pull request #26 from ahmedirfan1983/btor
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2014-02-12
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-12
Clifford Wolf
Added support for functions returning integer
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2014-02-12
Ahmed Irfan
modified btor synthesis script for correct use of splic...
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2014-02-12
Clifford Wolf
Disabled "abc -dff" in "make test" for now (waiting...
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