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yosys.git
2015-07-27
Clifford Wolf
Fixed "check" command for inout ports
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2015-07-25
Clifford Wolf
Some cleanups in opt_rmdff
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2015-07-25
Clifford Wolf
Added "miter -assert"
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2015-07-25
Clifford Wolf
Keep modules with $assume (like $assert)
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2015-07-24
Clifford Wolf
Improved $adff simplification
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2015-07-20
Clifford Wolf
iCE40 DFF sim models: init Q regs to 0
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2015-07-18
Clifford Wolf
Fixed techmap processes error msg
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2015-07-18
Clifford Wolf
Avoid tristate warning for blackbox ice40/cells_sim.v
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2015-07-16
Clifford Wolf
Some fixes in "select" command
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2015-07-10
Clifford Wolf
Fixed YosysJS.create_worker() usage of this.url_prefix
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2015-07-06
Clifford Wolf
Improved liberty file test case
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2015-07-06
Clifford Wolf
Updated ABC
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2015-07-06
Clifford Wolf
Do not collect disabled $memwr cells
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2015-07-04
Clifford Wolf
Improved YosysJS WebWorker API
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2015-07-03
Clifford Wolf
Bugfix in fsm_extract
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2015-07-02
Clifford Wolf
Added "synth -nofsm"
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-07-01
Clifford Wolf
Added opt_const -clkinv
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2015-06-30
Clifford Wolf
Added logic-loop error handling to freduce
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2015-06-29
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-06-29
Clifford Wolf
Bugfix in chparam
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2015-06-29
Clifford Wolf
Added design->rename(module, new_name)
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2015-06-28
Clifford Wolf
Added YosysJS.create_worker()
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2015-06-20
Clifford Wolf
iCE40: set min bram efficiency to 2%
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2015-06-20
Clifford Wolf
Using static mem size of 128 MB in emcc build
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2015-06-19
Clifford Wolf
Added init support to SMV back-end
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2015-06-19
Clifford Wolf
Progress in SMV back-end
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2015-06-19
Clifford Wolf
Progress in SMV back-end
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2015-06-18
Clifford Wolf
Progress in SMV back-end
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2015-06-17
Clifford Wolf
Progress in SMV back-end
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2015-06-17
Clifford Wolf
Added "rename -top new_name"
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2015-06-17
Clifford Wolf
Progress in SMV back-end
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2015-06-16
Clifford Wolf
Progress in SMV back-end
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2015-06-15
Clifford Wolf
Added "synth -nordff -noalumacc"
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2015-06-15
Clifford Wolf
Progress in SMV back-end
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2015-06-15
Clifford Wolf
Progress in SMV back-end
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2015-06-14
Clifford Wolf
Added "write_smv" skeleton
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2015-06-14
Clifford Wolf
Removed debug code from write_smt2
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2015-06-14
Clifford Wolf
Modernized memory_dff (and fixed a bug)
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2015-06-14
Clifford Wolf
Added "memory -nordff"
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2015-06-14
Clifford Wolf
Added write_smt2 -mem
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2015-06-11
Clifford Wolf
Makefile fix for YosysJS build
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2015-06-11
Clifford Wolf
Fixed cstr_buf for std::string with small string optimi...
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2015-06-11
Clifford Wolf
Improvements in cellaigs.cc and "json -aig"
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2015-06-10
Clifford Wolf
AigMaker refactoring
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2015-06-10
Clifford Wolf
Added "json -aig"
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2015-06-10
Clifford Wolf
Renamed "aig" to "aigmap"
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2015-06-10
Clifford Wolf
Fixed cellaigs port extending
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2015-06-09
Clifford Wolf
Added "aig" pass
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2015-06-09
Clifford Wolf
synth_ice40 now flattens by default
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2015-06-09
Clifford Wolf
Added cellaigs API
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2015-06-09
Clifford Wolf
Merge clock inverters in memory_dff
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2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
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2015-06-08
luke whittlesey
$mem cell in verilog backend : grouped writes by clock
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2015-06-08
Clifford Wolf
Fixed "avail_parameters" handling in module clone/copy
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2015-06-08
Clifford Wolf
Added log_dump() support for IdStrings
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2015-06-08
Clifford Wolf
Fixed handling of parameters with reversed range
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2015-06-04
luke whittlesey
Bug fix in $mem verilog backend + changed tests/bram...
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2015-05-31
Clifford Wolf
Added opt_share -share_all
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2015-05-31
Clifford Wolf
Added iCE40 PLL cells
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2015-05-31
Clifford Wolf
Added liberty dont_use support to dfflibmap
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2015-05-29
Clifford Wolf
Fixed signedness of genvar expressions
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2015-05-26
Clifford Wolf
Added output args to synth_ice40
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2015-05-24
Clifford Wolf
Improvements in BLIF front-end
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2015-05-23
Clifford Wolf
improved ice40 SB_IO sim model
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2015-05-23
Clifford Wolf
Improved "flatten" handlings of inout ports
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2015-05-23
Clifford Wolf
Added simple $dlatch support to opt_rmdff
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2015-05-23
Clifford Wolf
Added ice40 SB_IO sim model
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2015-05-22
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-05-22
Clifford Wolf
preserve used $-wires with init attribute in opt_clean
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2015-05-20
Clifford Wolf
Some fixes for $mem in verilog back-end
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2015-05-18
Clifford Wolf
bugfix in blif front-end
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2015-05-17
Clifford Wolf
added vloghtb test_febe.sh
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2015-05-17
Clifford Wolf
Improved .latch support in BLIF front-end
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2015-05-17
Clifford Wolf
Added read_blif command
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2015-05-17
Clifford Wolf
Generalized blifparse API
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2015-05-17
Clifford Wolf
abc/blifparse files reorganization
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2015-05-17
Clifford Wolf
Verific build fixes
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2015-05-13
Clifford Wolf
Added .barbuf support to abc BLIF parser
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2015-05-11
Clifford Wolf
changed file() to open() in python scripts
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2015-05-11
Clifford Wolf
Merge pull request #63 from wluker/verilog-backend-mem
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2015-05-11
luke whittlesey
Fixed bug in $mem cell verilog code generation.
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2015-05-10
Clifford Wolf
Disabled broken $mem support in verilog backend
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2015-05-10
Clifford Wolf
Merge pull request #62 from wluker/verilog-backend-mem
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2015-05-10
luke whittlesey
Made changes recommended by Clifford Wolf ...
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2015-05-08
luke whittlesey
Verilog backend for $mem cells should now be able to...
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2015-05-07
luke whittlesey
Added support for $mem cells in the verilog backend.
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2015-04-29
Clifford Wolf
Fixed memory_unpack for initialized memories
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2015-04-29
Clifford Wolf
Preserve important attributes in splitnets
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2015-04-29
Clifford Wolf
Added $eq/$neq -> $logic_not/$reduce_bool optimization
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2015-04-27
Clifford Wolf
ice40_opt bugfix
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2015-04-27
Clifford Wolf
iCE40: SB_CARRY const fold -> unmap SB_LUT
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2015-04-27
Clifford Wolf
Added simplemap $lut support
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2015-04-27
Clifford Wolf
Added iCE40 const folding support for SB_CARRY
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2015-04-26
Clifford Wolf
Initialization support for all iCE40 bram modes
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2015-04-25
Clifford Wolf
initialized iCE40 brams (mode 0)
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2015-04-25
Clifford Wolf
improved iCE40 SB_RAM40_4K simulation model
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2015-04-25
Clifford Wolf
Updated ABC to hg rev 779de2de1481
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2015-04-25
Clifford Wolf
More iCE40 bram improvements
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2015-04-24
Clifford Wolf
Improved attributes API and handling of "src" attributes
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