yosys.git
2014-01-30 Clifford WolfBugfix in name resolution with generate blocks
2014-01-30 Clifford WolfAdded yosys -H for command list
2014-01-29 Clifford Wolfpresentation progress
2014-01-29 Clifford Wolfpresentation progress
2014-01-29 Clifford WolfTiny change in example script in README
2014-01-29 Clifford WolfAdded -h command line option
2014-01-29 Clifford WolfAdded test comments to techlibs/cmos/cmos_cells.lib
2014-01-29 Clifford WolfUpdated ABC to hg rev e6b09e1
2014-01-28 Clifford WolfAdded read_verilog -icells option
2014-01-28 Clifford WolfMajor rewrite of techlibs/common/simlib.v for LEC ...
2014-01-28 Clifford Wolfpresentation progress
2014-01-28 Clifford WolfRenamed manual/FILES_* directories
2014-01-28 Clifford WolfProgress on presentation
2014-01-27 Clifford WolfProgress on presentation
2014-01-27 Clifford WolfAdded first presentation slides
2014-01-26 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198...
2014-01-26 Clifford WolfMerge pull request #21 from hansiglaser/master
2014-01-25 Johann Glaserenabled multiple "-map" for the extract pass
2014-01-25 Johann Glaserbeautified write_intersynth
2014-01-25 Ahmed Irfanroot bug corrected
2014-01-25 Clifford WolfAdded support for // comments in liberty parser
2014-01-24 Clifford WolfMerge branch 'btor'
2014-01-24 Ahmed Irfanremoved regex include
2014-01-24 Ahmed Irfanmerged clifford changes + removed regex
2014-01-24 Clifford WolfUse techmap -share_map in btor scripts
2014-01-24 Clifford WolfMoved btor scripts to backends/btor/
2014-01-24 Clifford WolfRestored Makefile
2014-01-24 Clifford WolfRestored IdString::check()
2014-01-24 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198...
2014-01-24 Clifford WolfFixed handling of unsized constants in verilog frontend
2014-01-24 Ahmed Irfanminor change in script
2014-01-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-20 Clifford WolfFixed algorithmic complexity of AST simplification...
2014-01-20 Ahmed Irfanslice bug corrected
2014-01-20 Ahmed Irfanassert feature
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded hilomap command
2014-01-19 Clifford WolfAdded sat -tempinduc and sat -prove-asserts
2014-01-19 Clifford WolfAdded $assert support to satgen
2014-01-19 Clifford WolfAdded $assert cell
2014-01-19 Clifford WolfAdded Verilog parser support for asserts
2014-01-18 Ahmed Irfanscript added
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-18 Clifford WolfFixed $lut simlib model for a wider range of tools
2014-01-18 Clifford WolfFixed parsing of verilog macros at end of line
2014-01-18 Clifford WolfMore changes to simlib to make it friendlier to a wider...
2014-01-18 Clifford WolfFixed a type in $mem model in simlib.v
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-18 Ahmed Irfanpmux2mux
2014-01-18 Clifford WolfRemoved cases of trailing comma in stdcells.v
2014-01-18 Clifford WolfAdded $bu0 cell to simlib.v
2014-01-18 Clifford WolfImproved setundef random number generator
2014-01-17 Clifford WolfAdded setundef command
2014-01-17 Clifford WolfSome improvements in log_dump_val_worker() templates
2014-01-17 Clifford WolfAdded techlibs/common/pmux2mux.v
2014-01-17 Ahmed Irfanverilog default options pull
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-17 Ahmed IrfanMerge pull request #4 from cliffordwolf/master
2014-01-17 Clifford WolfAdded verilog_defaults command
2014-01-17 Clifford WolfAdded support for $adff with undef data inputs to opt_rmdff
2014-01-17 Clifford WolfAdded select -assert-none and -assert-any
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-17 Ahmed IrfanMerge pull request #3 from cliffordwolf/master
2014-01-16 Clifford WolfAdded automatic memid generation to memory_unpack command
2014-01-16 Clifford WolfAdded memory_unpack command
2014-01-16 Ahmed Irfanslice error corrected
2014-01-15 Ahmed Irfanwidth issues
2014-01-15 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-15 Ahmed IrfanMerge pull request #2 from cliffordwolf/master
2014-01-14 Clifford WolfMerge pull request #20 from mschmoelzer/master
2014-01-14 Martin SchmölzerInclude unistd.h in passes/hierarchy/hierarchy.cc ...
2014-01-14 Clifford WolfAdded hierarchy -libdir option
2014-01-14 Clifford Wolfrenamed LibertyParer to LibertyParser
2014-01-14 Clifford WolfAdded "+" to list of liberty token characters
2014-01-14 Ahmed IrfanBTOR backend
2014-01-14 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-14 Ahmed IrfanMerge pull request #1 from cliffordwolf/master
2014-01-14 Clifford WolfAdded "opt_const -mux_undef"
2014-01-12 Clifford WolfFixed typo in frontends/ast/simplify.cc
2014-01-04 Clifford WolfImproved performance of freduce input cone reduction
2014-01-03 Clifford WolfImproved freduce performance on const signals
2014-01-03 Clifford WolfPerformance improvements in freduce pass
2014-01-03 Clifford WolfMore freduce cleanups
2014-01-03 Clifford WolfAdded updating of RTLIL::autoidx to ilang frontend
2014-01-03 Clifford WolfCleanups in freduce command
2014-01-03 Clifford WolfFixed SAT and ConstEval undef handling for $pmux and...
2014-01-03 Clifford WolfTiny cleanup in proc_mux.cc
2014-01-03 Ahmed Irfansplitnet -driver feature
2014-01-03 Clifford WolfAdded "splitnets -driver"
2014-01-03 Clifford WolfUse selection in freduce command
2014-01-03 Clifford WolfAnother small freduce cleanup/bugfix
2014-01-03 Clifford WolfAdded "connect" command
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-03 Ahmed Irfanmakefile
2014-01-03 Ahmed Irfanbtor
2014-01-03 Clifford WolfMore freduce cleanups and bugfixes
2014-01-03 Clifford WolfAdded RTLIL::SigSpec::optimized() API
2014-01-02 Clifford WolfAdded correct handling of $memwr priority
2014-01-02 Clifford WolfFixed more complex undef cases in freduce
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