yosys.git
2017-10-31 Clifford WolfAdd "ltp" command
2017-10-29 Clifford WolfFix SMT2 handling of initstate in sub-modules
2017-10-26 Clifford WolfFix memory corruption bug in opt_rmdff
2017-10-26 Clifford WolfFix typo in opt_clean log message
2017-10-25 Clifford WolfImprove smtio performance by using reader thread, not...
2017-10-25 Clifford WolfUse separate writer thread for talking to SMT solver...
2017-10-25 Clifford WolfImprove p_* functions in smtio.py
2017-10-25 Clifford WolfDisable OSX in .travis.yml
2017-10-25 Clifford WolfAdd ENABLE_DEBUG config flag
2017-10-25 Clifford WolfUpdate ABC to hg rev f6838749f234
2017-10-25 Clifford WolfRemove vhdl2verilog
2017-10-25 Clifford WolfCapsulate smt-solver read/write in separate functions
2017-10-25 Clifford WolfFix a bug in yosys-smtbmc in ROM handling
2017-10-20 Clifford WolfRemove PSL example from tests/sva/
2017-10-20 Clifford WolfRemove all PSL support code from verific.cc
2017-10-20 Clifford WolfMerge pull request #437 from mithro/master
2017-10-20 Tim 'mithro... Adding COPYING file with license information.
2017-10-14 Clifford WolfRevert 90be0d8 as it causes endless loops for some...
2017-10-13 Clifford WolfAdd "verific -vlog-libdir"
2017-10-13 Clifford WolfAdd "verific -vlog-incdir" and "verific -vlog-define"
2017-10-13 Clifford WolfUpdate Verific README
2017-10-12 Clifford WolfMerge pull request #434 from Kmanfi/vector_fix
2017-10-12 Kaj TuomiFix input vector for reduce cells.
2017-10-12 Clifford WolfAdd Verific fairness/liveness support
2017-10-11 Clifford WolfUpdate ABC to hg rev 6283c5d99b06
2017-10-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-10-10 Clifford WolfStart work on pre-processor for Verific SVA properties
2017-10-10 Clifford WolfRewrite ABC output to include proper net names in timin...
2017-10-10 Clifford WolfAdd timing constraints to osu035 example
2017-10-10 Clifford WolfRemove some dead code
2017-10-10 Clifford WolfAllow $past, $stable, $rose, $fell in $global_clock...
2017-10-07 Clifford WolfAdd $shiftx support to verilog front-end
2017-10-06 Clifford WolfUpdate ABC to hg rev 0fc1803a77c0
2017-10-05 Larry DoolittleClean whitespace and permissions in techlibs/intel
2017-10-05 Clifford WolfImprove handling of Verific errors
2017-10-04 Clifford WolfImprove Verific error handling, check VHDL static asserts
2017-10-04 Clifford WolfAdd blackbox command
2017-10-04 Clifford WolfFix nasty bug in Verific bindings
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github...
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:...
2017-10-03 Clifford WolfMerge branch 'dh73-master'
2017-10-03 Clifford WolfRename "write_verilog -nobasenradix" to "write_verilog...
2017-10-02 dh73Tested and working altsyncarm without init files
2017-10-01 dh73Fixed wrong declaration in Verilog backend
2017-10-01 dh73Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
2017-09-30 Udi FinkelsteinTurned a few member functions into const, esp. dumpAst...
2017-09-30 Udi FinkelsteinResolved classical Bison IF/THEN/ELSE shift/reduce...
2017-09-29 Clifford WolfAdd first draft of eASIC back-end
2017-09-29 Clifford WolfFix synth_ice40 doc regarding -top default
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-28 Clifford WolfMerge pull request #421 from stephengroat/osx-travis
2017-09-27 Stephendelete bad backslash
2017-09-27 Stephenforgot to install bundles
2017-09-27 Stephen GroatAdd osx tests using brew bundle
2017-09-27 Clifford WolfIncrease maximum LUT size in blifparse to 12 bits
2017-09-26 Udi Finkelstein$size() now works correctly for all cases!
2017-09-26 Udi Finkelstein$size() seems to work now with or without the optional...
2017-09-26 Clifford WolfParse reals as string in JSON front-end
2017-09-26 Clifford WolfMerge branch 'vlogpp-inc-fixes'
2017-09-26 Clifford WolfMinor coding style fix
2017-09-26 Clifford WolfMerge branch 'master' of https://github.com/combinatory...
2017-09-26 Udi Finkelsteinenable $bits() and $size() functions only when the...
2017-09-26 Udi FinkelsteinAdded $bits() for memories as well.
2017-09-26 Udi Finkelstein$size() now works with memories as well!
2017-09-26 Udi FinkelsteinAdd $size() function. At the moment it works only on...
2017-09-25 Clifford WolfFix ignoring of simulation timings so that invalid...
2017-09-21 combinatorylogicAdding support for string macros and macros with argume...
2017-09-16 Clifford WolfMerge pull request #413 from azonenberg/extract-reduce...
2017-09-16 Andrew ZonenbergAdded missing "break"
2017-09-15 Andrew ZonenbergImplemented off-chain support for extract_reduce
2017-09-15 Andrew Zonenbergextract_reduce now only removes the head of the chain...
2017-09-15 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-09-15 Clifford WolfUpdate ABC to hg rev cd6984ee82d4
2017-09-14 Clifford WolfMerge pull request #412 from azonenberg/reduce-fixes
2017-09-14 Robert Ouextract_reduce: Fix segfault on "undriven" inputs
2017-09-14 Clifford WolfMerge pull request #411 from azonenberg/counter-extract...
2017-09-14 Clifford WolfMerge pull request #410 from azonenberg/opt_demorgan
2017-09-14 Andrew ZonenbergMinor changes to opt_demorgan requested during code...
2017-09-14 Andrew ZonenbergFixed bug where counter extraction on non-GreenPAK...
2017-09-14 Andrew ZonenbergAdded support for inferring counters with reset to...
2017-09-14 Andrew ZonenbergAdded RESET_TO_MAX parameter to $__COUNT_ cell. Cannot...
2017-09-14 Andrew ZonenbergAdded support for inferring counters with active-low...
2017-09-14 Andrew ZonenbergInitial support for extraction of counters with clock...
2017-09-14 Andrew ZonenbergFixed typo in comment. Fixed bug where extract_counter...
2017-09-13 Andrew ZonenbergInitial version of opt_demorgan is functioning for...
2017-09-09 Clifford WolfAdd src attribute to extra cells generated by proc_dlatch
2017-09-09 Clifford WolfAdd src arguments to all cell creator helper functions
2017-09-02 Clifford WolfFurther improve extract_fa (but still buggy)
2017-09-02 Clifford WolfMerge pull request #406 from azonenberg/coolrunner...
2017-09-02 Clifford WolfMerge pull request #405 from azonenberg/gpak-refactoring
2017-09-01 Robert Oucoolrunner2: Finish fixing special-use p-terms
2017-09-01 Robert Oucoolrunner2: Generate a feed-through AND term when...
2017-09-01 Robert Oucoolrunner2: Initial fixes for special p-terms
2017-09-01 Robert Oucoolrunner2: Fix mapping of flip-flops
2017-09-01 Robert Oucoolrunner2: Combine some for loops together
2017-09-01 Andrew ZonenbergFixed typo in error message
2017-09-01 Andrew ZonenbergAdded blackbox $__COUNT_ cell model
2017-09-01 Andrew ZonenbergRefactoring: moved modules still in cells_sim to cells_...
2017-09-01 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
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