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yosys.git
2022-03-25
Miodrag Milanovic
Add -no-startoffset option to write_aiger
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2022-03-25
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2022-03-24
Miodrag Milanović
Merge pull request #3243 from nakengelhardt/fix_aiw_comment
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2022-03-24
N. Engelhardt
ignore # comment lines
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2022-03-23
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2022-03-22
Miodrag Milanovic
Update abc with latest fix
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2022-03-22
Miodrag Milanovic
Proper SigBit forming in sim
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2022-03-22
Miodrag Milanovic
Proper SigBit forming in sim
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2022-03-22
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2022-03-21
Marcelina Kościelnicka
xilinx: Add RAMB4* blackboxes
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2022-03-19
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2022-03-18
Miodrag Milanovic
More verbose warnings
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2022-03-17
Miodrag Milanović
Merge pull request #3236 from YosysHQ/micko/tb_initial
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2022-03-17
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2022-03-16
Miodrag Milanovic
Recognize registers and set initial state for them...
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2022-03-16
Miodrag Milanovic
Update sim help message.
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2022-03-15
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2022-03-14
YRabbit
gowin: add support for Double Data Rate primitives
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2022-03-14
Miodrag Milanović
Merge pull request #3232 from YosysHQ/micko/fst2tb
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2022-03-14
Miodrag Milanovic
Added fst2tb pass for generating testbench
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2022-03-14
Claire Xen
Merge pull request #3213 from antonblanchard/abc-typo
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2022-03-14
Miodrag Milanovic
Proper example code
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2022-03-12
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2022-03-11
Miodrag Milanović
Merge pull request #3229 from YosysHQ/micko/sim_date
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2022-03-11
Miodrag Milanović
Merge pull request #3222 from zachjs/prune-linux-ci
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2022-03-11
Miodrag Milanović
Merge pull request #3228 from YosysHQ/micko/disable_tests
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2022-03-11
Claire Xenia...
Add "sim -q" option
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2022-03-11
Miodrag Milanovic
Add date parameter to enable full date/time and version...
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2022-03-11
Claire Xenia...
Small fix in "sim" help message
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2022-03-11
Miodrag Milanović
Merge pull request #3226 from YosysHQ/micko/btor2witness
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2022-03-11
Miodrag Milanovic
FstData already do conversion to VCD
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2022-03-11
Miodrag Milanovic
Support cell name in btor witness file
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2022-03-11
Claire Xenia...
Fix handling of some formal cells in btor back-end
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2022-03-11
Miodrag Milanovic
handle state names of $anyconst and $anyseq
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2022-03-11
Zachary Snow
Prune Linux CI builds
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2022-03-11
Miodrag Milanovic
Proper write of memory data
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2022-03-10
Miodrag Milanovic
Disable tests on most of platforms
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2022-03-10
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2022-03-09
Lofty
intel_alm: M10K write-enable is negative-true
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2022-03-09
Miodrag Milanovic
Start work on memory init
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2022-03-09
Miodrag Milanovic
Fixes and error check
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2022-03-07
Miodrag Milanovic
cleanup
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2022-03-07
Miodrag Milanovic
Error checks for aiger witness
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2022-03-07
Miodrag Milanovic
btor2 witness co-simulation
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2022-03-07
Miodrag Milanović
Merge pull request #3210 from rqou/json-signed
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2022-03-05
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2022-03-04
Miodrag Milanović
Merge pull request #3186 from nakengelhardt/smtbmc_sby_...
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2022-03-04
Miodrag Milanović
Merge pull request #3206 from YosysHQ/micko/quote_remove
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2022-03-04
Miodrag Milanović
Merge pull request #3207 from nakengelhardt/json_escape...
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2022-03-04
Miodrag Milanovic
Next dev cycle
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2022-03-04
Miodrag Milanovic
Release version 0.15
yosys-0.15
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2022-03-04
Miodrag Milanovic
Update ABC
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2022-03-04
Miodrag Milanovic
Update documentation
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2022-03-04
Miodrag Milanović
Merge pull request #3219 from YosysHQ/micko/quick_vcd
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2022-03-04
Miodrag Milanović
Merge pull request #3220 from YosysHQ/claire/simstuff
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2022-03-03
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2022-03-02
Miodrag Milanovic
Add option to ignore X only signals in output
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2022-03-02
Miodrag Milanovic
Write simulation files after simulation is performed
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2022-03-02
Miodrag Milanovic
Update CHANGELOG
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2022-03-02
Claire Xen
Merge pull request #3224 from YosysHQ/micko/refactor
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2022-03-02
Miodrag Milanovic
Cleanup
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2022-03-01
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2022-02-28
Miodrag Milanovic
Refactor sim output writers
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2022-02-28
Miodrag Milanovic
Quick fix
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2022-02-28
Claire Xenia...
Add writing of aiw files to "sim" command
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2022-02-28
Claire Xenia...
Hotfix in AIGER witness reader state machine
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2022-02-28
Miodrag Milanovic
VCD reader support by using external tool
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2022-02-28
Miodrag Milanović
Merge pull request #3216 from YosysHQ/claire/simstuff
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2022-02-27
Miodrag Milanovic
Support extended aiw format
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2022-02-25
Miodrag Milanovic
Fix for last clock edge data
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2022-02-25
Claire Xenia...
Experimental sim changes
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2022-02-25
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2022-02-24
YRabbit
gowin: Remove unnecessary attributes
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2022-02-24
YRabbit
gowin: Add support for true differential output
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2022-02-23
Anton Blanchard
abc: Fix {I} and {P} substitution
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2022-02-22
N. Engelhardt
print cell name for properties in yosys-smtbmc
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2022-02-22
Claire Xen
Merge pull request #3211 from YosysHQ/micko/witness
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2022-02-22
Claire Xen
Merge pull request #3197 from YosysHQ/claire/smtbmcfix
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2022-02-22
R
json: Add help message for `signed` field
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2022-02-22
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2022-02-21
Miodrag Milanović
Merge pull request #3203 from YosysHQ/micko/sim_ff
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2022-02-21
Marcelina Kościelnicka
ecp5: Do not use specify in generate in cells_sim.v.
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2022-02-21
Miodrag Milanovic
Fix handling of ce_over_srst
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2022-02-18
N. Engelhardt
fix handling of escaped chars in json backend and frontend
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2022-02-18
Claire Xenia...
Fix cycle 0 in aiger witness co-simulation
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2022-02-18
Miodrag Milanovic
Changed error message
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2022-02-18
Miodrag Milanovic
Added AIGER witness file co simulation
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2022-02-18
Miodrag Milanovic
simplify logic of handling flip-flops and latches
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2022-02-17
Miodrag Milanovic
Review cleanup
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2022-02-16
Miodrag Milanovic
Remove quotes if any from attribute
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2022-02-16
Miodrag Milanovic
test dlatchsr and adlatch
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2022-02-16
Miodrag Milanovic
Added test cases
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2022-02-16
Miodrag Milanovic
Add support for various ff/latch cells simulation
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2022-02-16
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2022-02-15
Miodrag Milanović
Merge pull request #3204 from YosysHQ/claire/update-abc
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2022-02-15
Miodrag Milanovic
Bump ABC version
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2022-02-15
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2022-02-14
Zachary Snow
verilog: support for time scale delay values
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2022-02-14
Kamil Rakoczy
Fix access to whole sub-structs (#3086)
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2022-02-13
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