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yosys.git
2018-12-11 Graham Edgecombememory_bram: Fix initdata bit order after shuffling commit | commitdiff | tree
2018-12-08 Clifford WolfAdd "yosys-smtbmc --btorwit" skeleton commit | commitdiff | tree
2018-12-08 Clifford WolfFix btor init value handling commit | commitdiff | tree
2018-12-07 David ShahMerge pull request #727 from whitequark/opt_lut commit | commitdiff | tree
2018-12-07 whitequarkopt_lut: leave intact LUTs with cascade feeding module... commit | commitdiff | tree
2018-12-07 whitequarkopt_lut: show original truth table for both cells. commit | commitdiff | tree
2018-12-07 whitequarkopt_lut: add -limit option, for debugging misoptimizations. commit | commitdiff | tree
2018-12-06 Clifford WolfAdd missing .gitignore commit | commitdiff | tree
2018-12-06 Clifford WolfBugfix in opt_expr handling of a<0 and a>=0 commit | commitdiff | tree
2018-12-06 Clifford WolfVerific updates commit | commitdiff | tree
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708 commit | commitdiff | tree
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut commit | commitdiff | tree
2018-12-05 whitequarksynth_ice40: add -noabc option, to use built-in LUT... commit | commitdiff | tree
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to... commit | commitdiff | tree
2018-12-05 whitequarkFix typo. commit | commitdiff | tree
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master commit | commitdiff | tree
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support commit | commitdiff | tree
2018-12-05 Clifford WolfRename opt_lut.cpp to opt_lut.cc commit | commitdiff | tree
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut commit | commitdiff | tree
2018-12-05 Clifford WolfMerge pull request #716 from whitequark/ice40_unlut commit | commitdiff | tree
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such... commit | commitdiff | tree
2018-12-05 whitequarkopt_lut: always prefer to eliminate 1-LUTs. commit | commitdiff | tree
2018-12-05 whitequarkopt_lut: collect and display statistics. commit | commitdiff | tree
2018-12-05 whitequarkopt_lut: refactor to use a worker. NFC. commit | commitdiff | tree
2018-12-05 whitequarksynth_ice40: add -relut option, to run ice40_unlut... commit | commitdiff | tree
2018-12-05 whitequarkopt_lut: new pass, to combine LUTs for tighter packing. commit | commitdiff | tree
2018-12-05 whitequarkExtract ice40_unlut pass from ice40_opt. commit | commitdiff | tree
2018-12-05 Serge BazanskiMerge pull request #719 from YosysHQ/q3k/flailing-aroun... commit | commitdiff | tree
2018-12-05 Sergiusz Bazanskitravis/osx: fix, use clang instead of gcc commit | commitdiff | tree
2018-12-04 Clifford WolfFix typo commit | commitdiff | tree
2018-12-04 Clifford WolfMerge pull request #702 from smunaut/min_ce_use commit | commitdiff | tree
2018-12-04 Diego HChanges in GoWin synth commands and ALU primitive support commit | commitdiff | tree
2018-12-02 Miodrag MilanovicLeave only real black box cells commit | commitdiff | tree
2018-12-01 Miodrag MilanovicInitial support for Anlogic FPGA commit | commitdiff | tree
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master commit | commitdiff | tree
2018-11-29 Clifford WolfImprove ConstEval error handling for non-eval cell... commit | commitdiff | tree
2018-11-27 Sylvain Munautice40: Add option to only use CE if it'd be use by... commit | commitdiff | tree
2018-11-27 Sylvain Munautdff2dffe: Add option for unmap to only remove DFFE... commit | commitdiff | tree
2018-11-24 Sylvain MunautMake return value of $clog2 signed commit | commitdiff | tree
2018-11-20 Clifford WolfAdd iteration limit to "opt_muxtree" commit | commitdiff | tree
2018-11-13 Clifford WolfUpdate ABC to git rev 2ddc57d commit | commitdiff | tree
2018-11-12 Clifford WolfAdd "write_aiger -I -O -B" commit | commitdiff | tree
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys commit | commitdiff | tree
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7 commit | commitdiff | tree
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb commit | commitdiff | tree
2018-11-11 Clifford WolfUpdate ABC to git rev 68da3cf commit | commitdiff | tree
2018-11-10 Eddie HungAdd support for Xilinx PS7 block commit | commitdiff | tree
2018-11-09 Clifford WolfSet Verific flag vhdl_support_variable_slice=1 commit | commitdiff | tree
2018-11-09 David Shahecp5: Add 'fake' DCU parameters commit | commitdiff | tree
2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells commit | commitdiff | tree
2018-11-09 Clifford WolfMerge pull request #696 from arjenroodselaar/verific_darwin commit | commitdiff | tree
2018-11-08 Clifford WolfFix "make ystests" to use correct Yosys binary commit | commitdiff | tree
2018-11-08 Arjen RoodselaarUse appropriate static libraries when building with... commit | commitdiff | tree
2018-11-07 Clifford WolfMerge pull request #693 from YosysHQ/rlimit commit | commitdiff | tree
2018-11-07 David Shahecp5: Adding some blackbox cells commit | commitdiff | tree
2018-11-07 Clifford WolfLimit stack size to 16 MB on Darwin commit | commitdiff | tree
2018-11-06 Clifford WolfMerge pull request #694 from trcwm/dffmap_expr_fix commit | commitdiff | tree
2018-11-06 Niels MoseleyDFFLIBMAP: changed 'missing pin' error into a warning... commit | commitdiff | tree
2018-11-06 Clifford WolfRun solver in non-incremental mode whem smtio.py is... commit | commitdiff | tree
2018-11-06 Clifford WolfUpdate ABC rev to 4d56acf commit | commitdiff | tree
2018-11-06 Clifford WolfFix for improved smtio.py rlimit code commit | commitdiff | tree
2018-11-06 Clifford WolfImprove stack rlimit code in smtio.py commit | commitdiff | tree
2018-11-05 Clifford WolfAllow square brackets in liberty identifiers commit | commitdiff | tree
2018-11-05 Clifford WolfMerge pull request #691 from arjenroodselaar/stacksize commit | commitdiff | tree
2018-11-05 Arjen RoodselaarUse conservative stack size for SMT2 on MacOS commit | commitdiff | tree
2018-11-04 Clifford WolfAdd warning for SV "restrict" without "property" commit | commitdiff | tree
2018-11-04 Clifford WolfAdd proper error message for when smtbmc "append" fails commit | commitdiff | tree
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space... commit | commitdiff | tree
2018-11-04 Clifford WolfMerge pull request #687 from trcwm/master commit | commitdiff | tree
2018-11-04 Clifford WolfMerge pull request #688 from ZipCPU/rosenfell commit | commitdiff | tree
2018-11-03 ZipCPUMake and dependent upon LSB only commit | commitdiff | tree
2018-11-03 Niels MoseleyLiberty file newline handling is more relaxed. More... commit | commitdiff | tree
2018-11-03 Niels MoseleyReport an error when a liberty file contains pin refere... commit | commitdiff | tree
2018-11-01 Clifford WolfDo not generate "reg assigned in a continuous assignmen... commit | commitdiff | tree
2018-11-01 Clifford WolfAdd support for signed $shift/$shiftx in smt2 back-end commit | commitdiff | tree
2018-10-31 Clifford WolfMerge branch 'igloo2' commit | commitdiff | tree
2018-10-31 Clifford WolfFix sf2 LUT interface commit | commitdiff | tree
2018-10-31 Clifford WolfBasic SmartFusion2 and IGLOO2 synthesis support commit | commitdiff | tree
2018-10-30 Clifford WolfMerge pull request #680 from jburgess777/fix-empty... commit | commitdiff | tree
2018-10-28 Jon BurgessAvoid assert when label is an empty string commit | commitdiff | tree
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master commit | commitdiff | tree
2018-10-25 Clifford WolfFix minor typo in error message commit | commitdiff | tree
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error commit | commitdiff | tree
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the... commit | commitdiff | tree
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp commit | commitdiff | tree
2018-10-22 whentzefix unhandled std::out_of_range when calling yosys... commit | commitdiff | tree
2018-10-22 David Shahecp5: Remove DSP parameters that don't work commit | commitdiff | tree
2018-10-21 rafaeltpusing [i] to access individual bits of SigSpec and... commit | commitdiff | tree
2018-10-21 David Shahecp5: Add DSP blackboxes commit | commitdiff | tree
2018-10-21 rafaeltpcleaning up for PR commit | commitdiff | tree
2018-10-21 rafaeltpfixing code style commit | commitdiff | tree
2018-10-21 rafaeltpsolves #675 commit | commitdiff | tree
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master commit | commitdiff | tree
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning commit | commitdiff | tree
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface... commit | commitdiff | tree
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments commit | commitdiff | tree
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the... commit | commitdiff | tree
2018-10-20 Ruben UndheimFixed memory leak commit | commitdiff | tree
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve commit | commitdiff | tree
2018-10-19 David Shahecp5: Sim model fixes commit | commitdiff | tree
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