| 2010-08-18 |
Andrew Waterman | [sim] integrated SoftFloat-3 with ISA sim; removed... |
commit | commitdiff | tree |
| 2010-08-18 |
Andrew Waterman | [sim] specialized softfloat for riscv |
commit | commitdiff | tree |
| 2010-08-18 |
Andrew Waterman | [sim] added riscv folder to softfloat |
commit | commitdiff | tree |
| 2010-08-18 |
Andrew Waterman | [sim] added SoftFloat-3 source |
commit | commitdiff | tree |
| 2010-08-10 |
Andrew Waterman | [xcc,sim] implement FP using softfloat |
commit | commitdiff | tree |
| 2010-08-10 |
Andrew Waterman | [sim] removed unused elf loader |
commit | commitdiff | tree |
| 2010-08-09 |
Andrew Waterman | [sim] added softfloat |
commit | commitdiff | tree |
| 2010-08-06 |
Andrew Waterman | [sim,xcc] Added first few Hauser FP insns (sign-injection) |
commit | commitdiff | tree |
| 2010-08-05 |
Andrew Waterman | [sim] Bug fixes in shifts, plus a new test case |
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| 2010-08-05 |
Andrew Waterman | [xcc] Removed ctc1, cfc1 instructions; added fp move... |
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| 2010-08-05 |
Andrew Waterman | [xcc,pk,sim] Added first part of FP support |
commit | commitdiff | tree |
| 2010-08-04 |
Andrew Waterman | [sim,xcc] removed sll32/srl32/sra32 opcodes |
commit | commitdiff | tree |
| 2010-08-04 |
Andrew Waterman | [pk,sim,xcc] Renamed instructions to RISC-V spec |
commit | commitdiff | tree |
| 2010-07-29 |
Andrew Waterman | [gcc] generate code for complex branches |
commit | commitdiff | tree |
| 2010-07-29 |
Andrew Waterman | [sim,xcc] Changed instruction format to RISC-V |
commit | commitdiff | tree |
| 2010-07-23 |
Yunsup Lee | [sim] various fixes to get the sim work with the fesvr |
commit | commitdiff | tree |
| 2010-07-22 |
Andrew Waterman | [pk,sim] removed cop0 console i/o support |
commit | commitdiff | tree |
| 2010-07-22 |
Andrew Waterman | [pk,sim] first cut of appserver communication link |
commit | commitdiff | tree |
| 2010-07-20 |
Andrew Waterman | [pk,sim] added temporary "exit" functionality |
commit | commitdiff | tree |
| 2010-07-19 |
Andrew Waterman | Reorganized directory structure |
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projects / riscv-isa-sim.git / shortlog