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yosys.git
2019-11-15
David Shah
ecp5: Use new autoname pass for better cell/net names
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2019-11-14
Clifford Wolf
Merge pull request #1490 from YosysHQ/clifford/autoname
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2019-11-14
Clifford Wolf
Merge pull request #1444 from btut/feature/python_wrapp...
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2019-11-14
Clifford Wolf
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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2019-11-14
Clifford Wolf
Merge branch 'makaimann-label-bads-btor'
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2019-11-14
Clifford Wolf
Use cell name for btor bad state props when it is a...
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2019-11-14
Clifford Wolf
Merge branch 'label-bads-btor' of https://github.com...
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2019-11-13
Clifford Wolf
Add "autoname" pass and use it in "synth_ice40"
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2019-11-13
whitequark
Merge pull request #1488 from whitequark/flowmap-fixes
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2019-11-13
Clifford Wolf
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
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2019-11-12
Clifford Wolf
Update fsm_detect bugfix
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2019-11-12
Clifford Wolf
Bugfix in fsm_detect
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2019-11-12
Clifford Wolf
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne
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2019-11-12
Makai Mann
Add an info string symbol for bad states in btor backend
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2019-11-12
whitequark
flowmap: when doing mincut, ensure source is always...
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2019-11-11
whitequark
flowmap: don't break if that creates a k+2 (and larger...
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2019-11-11
Miodrag Milanovic
Fixed tests
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2019-11-11
Clifford Wolf
Do not map $eq and $ne in cmp2lut, only proper arithmet...
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2019-11-10
Clifford Wolf
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
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2019-11-07
Clifford Wolf
Add check for valid macro names in macro definitions
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2019-11-06
Marcin Kościelnicki
synth_xilinx: Merge blackbox primitive libraries.
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2019-11-04
Clifford Wolf
Fix write_aiger bug added in 524af21
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2019-10-31
Clifford Wolf
Add CodingReadme section on script passes
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2019-10-27
Clifford Wolf
Merge pull request #1393 from whitequark/write_verilog...
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2019-10-24
Clifford Wolf
Improve naming scheme for (VHDL) modules imported from...
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2019-10-24
David Shah
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
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2019-10-24
Clifford Wolf
Add "verific -L"
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2019-10-23
David Shah
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
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2019-10-23
David Shah
ice40: Support for post-pnr timing simulation
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2019-10-23
David Shah
xilinx: Add URAM288 mapping for xcup
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2019-10-23
David Shah
xilinx: Add support for UltraScale[+] BRAM mapping
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2019-10-22
Clifford Wolf
Bugfix in smtio vcd handling of $-identifiers
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2019-10-22
Marcin Kościelnicki
xilinx: Support multiplier mapping for all families.
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2019-10-22
Clifford Wolf
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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2019-10-21
Clifford Wolf
Add "verilog_defines -list" and "verilog_defines -reset"
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2019-10-21
Clifford Wolf
Fix handling of "restrict" in Verific front-end
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2019-10-20
David Shah
ecp5: Pass -nomfs to abc9
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2019-10-19
Miodrag Milanović
Merge pull request #1457 from xobs/python-binary-name
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2019-10-19
Sean Cross
Makefile: don't assume python is called `python3`
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2019-10-18
Miodrag Milanović
Merge pull request #1454 from YosysHQ/mmicko/common_tests
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2019-10-18
Miodrag Milanovic
fixed error
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2019-10-18
Miodrag Milanovic
Unify verilog style
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2019-10-18
Miodrag Milanovic
Common memory test now shared
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2019-10-18
Miodrag Milanovic
Remove not needed tests
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2019-10-18
Miodrag Milanovic
Share common tests
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2019-10-18
Miodrag Milanovic
fix yosys path
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2019-10-18
Miodrag Milanovic
Fix path to yosys
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2019-10-18
Miodrag Milanovic
Moved all tests in arch sub directory
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2019-10-18
Miodrag Milanovic
Add async2sync
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2019-10-18
Miodrag Milanović
Merge pull request #1435 from YosysHQ/mmicko/efinix
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2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/efinix
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2019-10-18
Miodrag Milanović
Merge pull request #1434 from YosysHQ/mmicko/anlogic
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2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/anlogic
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2019-10-18
Miodrag Milanović
Merge pull request #1421 from YosysHQ/eddie/pr1352
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2019-10-18
Miodrag Milanović
Merge branch 'master' into eddie/pr1352
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2019-10-18
Miodrag Milanović
Merge pull request #1420 from YosysHQ/eddie/pr1363
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-17
N. Engelhardt
Call memory_dff before DSP mapping to reserve registers...
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2019-10-17
Miodrag Milanovic
Make equivalence work with latest master
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2019-10-17
Miodrag Milanovic
remove not needed top module
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2019-10-17
Miodrag Milanovic
remove not needed top module
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2019-10-17
Miodrag Milanovic
split muxes synth per type
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2019-10-17
Miodrag Milanovic
Test dffs separetely
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2019-10-17
Miodrag Milanovic
Split latches into separete tests
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2019-10-17
Miodrag Milanovic
Fix formatting
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2019-10-17
Miodrag Milanovic
Clean verilog code from not used define block
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2019-10-17
Miodrag Milanovic
Removed alu and div_mod test as agreed, ignore generate...
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2019-10-17
Miodrag Milanovic
Test per flip-flop type
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2019-10-17
Eddie Hung
Add -assert
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2019-10-17
Eddie Hung
Use built-in async2sync call as per #1417
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2019-10-17
Eddie Hung
Update mul test to DSP48E1
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2019-10-17
Eddie Hung
Update area for div_mod
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2019-10-17
Eddie Hung
Add comment for lack of tristate logic pointing to...
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2019-10-17
Eddie Hung
Move $x to end as 7f0eec8
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2019-10-17
SergeyDegtyar
adffs test update (equiv_opt -multiclock)
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
Sergey
Fix div_mod test
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2019-10-17
SergeyDegtyar
Add comment with expected behavior for latches,tribuf...
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2019-10-17
SergeyDegtyar
Fix latches.ys test
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2019-10-17
SergeyDegtyar
Remove xilinx_ug901 tests (will be moved to yosys-tests)
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2019-10-17
SergeyDegtyar
Add smoke tests to tests/xilinx
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2019-10-17
SergeyDegtyar
Add comments for unproven cells.
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2019-10-17
SergeyDegtyar
Add tests for Xilinx UG901 examples
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2019-10-16
Clifford Wolf
Merge pull request #1450 from YosysHQ/clifford/fixdffmux
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2019-10-16
Clifford Wolf
Fix dffmux peepopt init handling
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2019-10-16
Clifford Wolf
Move GENERATE_PATTERN macro to separate utility header
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2019-10-16
Clifford Wolf
Disable left-over log_debug in peepopt_dffmux.pmg
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2019-10-16
Clifford Wolf
Fix parsing of .cname BLIF statements
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2019-10-15
Clifford Wolf
Add .blackbox support to blif front-end
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2019-10-15
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-14
Clifford Wolf
Merge pull request #1448 from YosysHQ/daveshah1-sv...
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2019-10-14
David Shah
Merge pull request #1446 from YosysHQ/dave/ecp5-ioff
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2019-10-14
Clifford Wolf
Use "(id)" instead of "id" for types as temporary hack
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