microwatt.git
2019-08-29 Anton BlanchardArty A7 reset pin is C2
2019-08-29 Anton BlanchardMerge pull request #7 from riktw/fusesoc_arty_a7
2019-08-29 Anton BlanchardMerge pull request #9 from antonblanchard/travis-fix
2019-08-29 Anton BlanchardA few Travis CI fixes
2019-08-29 riktwAdded support for building for Arty A7 boards
2019-08-28 Anton BlanchardMerge pull request #5 from antonblanchard/travis-test
2019-08-28 Anton BlanchardAdd an initial travis.yml
2019-08-28 Anton BlanchardAdd srd and srw
2019-08-28 Anton BlanchardAdd sim only divw
2019-08-27 Anton BlanchardFix ghdl build error with pp_soc_memory
2019-08-27 Anton Blanchardmicropython only requires 512kB of BRAM
2019-08-27 Anton BlanchardMerge pull request #6 from mikey/gif
2019-08-27 Anton BlanchardAdd -Wall to CFLAGS
2019-08-27 Michael NeulingAdd pretty gif demo of MicroPython on Microwatt to...
2019-08-26 Anton BlanchardAdd missing argument to fprintf warning
2019-08-26 Anton BlanchardAdd some initial FPGA synthesis instructions
2019-08-26 Anton BlanchardRebuild hello world assuming a 50MHz clock
2019-08-26 Anton BlanchardMerge pull request #3 from olofk/plle2
2019-08-26 Olof KindgrenAdd and use plle2 primitive for nexys boards
2019-08-26 Anton BlanchardMerge pull request #4 from sharkcz/build
2019-08-24 Dan Horákdon't cross compile when on Power
2019-08-23 Anton BlanchardAdd a simple hello_world example that also echos input
2019-08-23 Anton BlanchardMerge pull request #2 from olofk/fusesoc_nexys_a7
2019-08-23 Olof KindgrenAdded synthesis target
2019-08-23 Olof KindgrenAdd Nexys Video support
2019-08-23 Olof KindgrenAdd FuseSoC core description file with Nexys A7 support
2019-08-23 Olof KindgrenAdd constraint file for Nexys A7
2019-08-23 Olof KindgrenExpose ram init file and memory size through toplevel
2019-08-23 Olof KindgrenAdd dummy clock generator
2019-08-23 Anton BlanchardAdd a few more FPGA related files
2019-08-22 Anton BlanchardInitial import of microwatt