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yosys.git
2016-07-12
whitequark
write_json: also write module attributes.
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2016-07-11
Clifford Wolf
Yosys-smtbmc: Support for hierarchical VCD dumping
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2016-07-11
Clifford Wolf
Moved smt2 yosys info parsing from smtbmc.py to smtio.py
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2016-07-11
Clifford Wolf
Added "prep -auto-top" and "synth -auto-top"
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2016-07-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-10
Clifford Wolf
Merge pull request #189 from whitequark/master
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2016-07-10
Clifford Wolf
Support for hierarchical designs in smt2 back-end
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2016-07-10
whitequark
greenpak4: add GP_COUNT{8,14}_ADV cells.
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2016-07-09
Clifford Wolf
Further improved fsm_detect output, attempt to detect...
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2016-07-09
Clifford Wolf
Added printing of some warning messages to fsm_detect
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2016-07-08
Clifford Wolf
Added warning about adding fsm_encoding attributes...
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2016-07-08
Clifford Wolf
Minor fixes in ice40_ff* passes for sloppy SB_DFF insta...
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2016-07-08
Clifford Wolf
Fixed mem assignment in left-hand-side concatenation
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2016-07-08
Clifford Wolf
Merge branch 'eddiehung-vtr'
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2016-07-08
Clifford Wolf
Restored blif "-true - .." behavior, use "-true + ...
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2016-07-08
Clifford Wolf
In BLIF, a .names without entries already always outputs 0
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2016-07-08
Clifford Wolf
Undo eddiehung-vtr Makefile changes
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-07-02
Clifford Wolf
Fixed autotest.sh handling of `timescale
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2016-07-01
Clifford Wolf
Merge branch 'assert-limit'
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2016-07-01
Clifford Wolf
Replaced "select -assert-limit" with -assert-max and...
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2016-07-01
eshellko
Added 'assert-limit' option for 'select' command
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2016-06-30
Clifford Wolf
Improved ice40_ffinit error reporting
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2016-06-21
Clifford Wolf
Merge pull request #181 from rubund/input_logic_allowed
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2016-06-20
Ruben Undheim
Allow defining input ports as "input logic" in SystemVe...
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2016-06-19
Clifford Wolf
Bugfix in "abc -script" handling
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2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
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2016-06-19
Clifford Wolf
Added "deminout"
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2016-06-18
Ruben Undheim
A few modifications after pull request comments
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2016-06-18
Clifford Wolf
Added "read_blif -sop"
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2016-06-18
Clifford Wolf
Added $sop support to BLIF back-end
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2016-06-18
Ruben Undheim
Added support for SystemVerilog packages with localpara...
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2016-06-17
Clifford Wolf
Added "dc2" to default ABC scripts
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2016-06-17
Clifford Wolf
Fixed init issue in mem2reg_test2 test case
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2016-06-17
Clifford Wolf
Added "abc -I <num> -P <num>"
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2016-06-17
Clifford Wolf
Added $sop SAT model
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2016-06-17
Clifford Wolf
Improved support for $sop cells
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2016-06-17
Clifford Wolf
Added $sop cell type and "abc -sop"
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2016-06-17
Clifford Wolf
Updated ABC to hg rev b5df6e2b76f0
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2016-06-09
Clifford Wolf
Added "nlutmap -assert"
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2016-06-08
Clifford Wolf
Do not run "wreduce" in "prep -ifx"
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2016-06-06
Clifford Wolf
Added "proc_mux -ifx"
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2016-06-03
Clifford Wolf
Added "setundef -init"
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2016-06-02
Clifford Wolf
Fix all undef-muxes in dlatch input cone
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2016-06-01
Clifford Wolf
Avoid creating undef-muxes when inferring latches in...
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2016-05-29
Clifford Wolf
Added opt_expr support for div/mod by power-of-two
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2016-05-27
Clifford Wolf
Fixed procedural assignments to non-unique lvalues...
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2016-05-27
Clifford Wolf
Fixed access-after-delete bug in mem2reg code
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2016-05-27
Clifford Wolf
fixed typos in error messages
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2016-05-27
Clifford Wolf
Fixed "scc" for cells that have feedback singals _and_...
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2016-05-22
Clifford Wolf
Merge pull request #172 from zeldin/deterministic_hierarchy
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2016-05-22
Marcus Comstedt
Made the expansion order of hierarchy deterministic
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2016-05-20
Clifford Wolf
Some fixes in tests/asicworld/*_tb.v
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2016-05-20
Clifford Wolf
Improvements and fixes in autotest.sh script and test_a...
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2016-05-20
Clifford Wolf
Merge branch 'master' of https://github.com/Kmanfi...
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2016-05-20
Clifford Wolf
Also escape "=" in spice output
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2016-05-20
Clifford Wolf
Small improvements in Verilog front-end docs
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2016-05-19
Kaj Tuomi
Close opened dump file.
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2016-05-19
Kaj Tuomi
Fix for Modelsim transcript line warp issue #164
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2016-05-14
Clifford Wolf
Don't sign-extend memory bram initialization data
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2016-05-14
Clifford Wolf
Added missing "#define HASHLIB_H"
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2016-05-14
Clifford Wolf
Minor presentation fixes
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2016-05-11
Clifford Wolf
Updated min GCC requirement to GCC 4.8
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2016-05-09
Clifford Wolf
Added manual download link to README
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2016-05-08
Clifford Wolf
Include <cmath> in yosys.h
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2016-05-08
Clifford Wolf
Merge pull request #162 from azonenberg/master
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2016-05-08
Andrew Zonenberg
Added GP_DELAY cell
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2016-05-08
Andrew Zonenberg
Fixed typo in port name
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2016-05-08
Andrew Zonenberg
Fixed extra semicolon
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2016-05-08
Andrew Zonenberg
Fixed typo in parameter name
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2016-05-08
Andrew Zonenberg
Added simulation timescale declaration
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2016-05-07
Clifford Wolf
Fixes for MXE build
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2016-05-07
Clifford Wolf
Added support for "keep" attribute to shregmap
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2016-05-06
Clifford Wolf
Added synth_ice40 support for latches via logic loops
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2016-05-06
Clifford Wolf
Added "write_blif -noalias"
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2016-05-06
Clifford Wolf
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
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2016-05-06
Clifford Wolf
Fixed preservation of important attributes in techmap
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2016-05-05
Clifford Wolf
Merge pull request #159 from azonenberg/master
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2016-05-05
Andrew Zonenberg
Changed order of passes for better handling of INIT...
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2016-05-05
Andrew Zonenberg
Changed port names in greenpak shregmap
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2016-05-05
Andrew Zonenberg
Renamed module parameter
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2016-05-04
Andrew Zonenberg
Refactored synth_greenpak4 to use iopadmap for mapping...
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2016-05-04
Clifford Wolf
Added tristate buffer support to iopadmap
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2016-05-04
Clifford Wolf
Merge pull request #157 from azonenberg/master
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2016-05-04
Andrew Zonenberg
Fixed incorrect signal naming in GP_IOBUF
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2016-05-04
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-05-04
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-05-04
Clifford Wolf
Fixed iopadmap attribute handling
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2016-05-04
Andrew Zonenberg
Added tri-state I/O extraction for GreenPak
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2016-05-04
Andrew Zonenberg
Added GreenPak I/O buffer cells
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2016-05-03
Andrew Zonenberg
Added comment to clarify GP_ABUF cell
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2016-05-03
Andrew Zonenberg
Added GP_ABUF cell
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2016-05-02
Clifford Wolf
Merge pull request #154 from azonenberg/master
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2016-05-01
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-29
Clifford Wolf
Improved TCL_VERSION detection so it does not read...
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2016-04-29
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-28
Clifford Wolf
Added "qwp -v"
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2016-04-28
Andrew Zonenberg
Added GP_PGA cell
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2016-04-26
Clifford Wolf
Connections between inputs and inouts are driven by...
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2016-04-25
Clifford Wolf
Fixed test_autotb for modules with many cell ports
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