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yosys.git
2019-10-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-03
Eddie Hung
English
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2019-10-03
Clifford Wolf
Change smtbmc "Warmup failed" status to "PREUNSAT"
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2019-10-03
Clifford Wolf
Update ABC to git rev 623b5e8
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2019-10-03
Clifford Wolf
Bump version
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2019-10-03
Clifford Wolf
Merge pull request #1419 from YosysHQ/eddie/lazy_derive
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2019-10-03
Clifford Wolf
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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2019-10-03
Clifford Wolf
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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2019-10-03
Clifford Wolf
Add "check -allow-tbuf"
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2019-10-03
David Shah
Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16
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2019-10-03
Eddie Hung
Merge pull request #1423 from YosysHQ/eddie/techmap_rep...
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2019-10-03
Eddie Hung
log_dump() to support State enum
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2019-10-02
Eddie Hung
Also rename cells with _TECHMAP_REPLACE_. prefix, as...
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2019-10-02
Eddie Hung
Extend test with renaming cells with prefix too
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2019-10-02
Clifford Wolf
Merge pull request #1428 from YosysHQ/clifford/fixbtor
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2019-10-02
Clifford Wolf
Add "check -mapped"
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2019-10-02
Clifford Wolf
Fix btor back-end to use "state" instead of "input...
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2019-10-01
Eddie Hung
More fixes
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2019-10-01
Eddie Hung
Escape Verilog identifiers for legality outside of...
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2019-10-01
Miodrag Milanović
Merge pull request #1426 from YosysHQ/mmicko/fix_environ
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2019-10-01
Miodrag Milanovic
Define environ, fixes #1424
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2019-10-01
David Shah
ecp5: Fix shuffle_enable port
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2019-10-01
David Shah
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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2019-10-01
Eddie Hung
Add test
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2019-10-01
Eddie Hung
techmap wires named _TECHMAP_REPLACE_.<identifier>...
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2019-10-01
Eddie Hung
No need to punch ports at all
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2019-09-30
Eddie Hung
Resolve FIXME on calling proc just once
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2019-09-30
Eddie Hung
Cleanup $currQ from aigerparse
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2019-09-30
Eddie Hung
Remove need for $currQ port connection
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2019-09-30
Eddie Hung
Add explanation to abc_map.v
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2019-09-30
Eddie Hung
Add quick test
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2019-09-30
Eddie Hung
Add -select option to aigmap
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2019-09-30
Eddie Hung
Cleanup
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2019-09-30
Eddie Hung
Add comment
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2019-09-30
Eddie Hung
Fix typo
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2019-09-30
Eddie Hung
Fix for svinterfaces
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2019-09-30
Eddie Hung
module->derive() to be lazy and not touch ast if alread...
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2019-09-30
Eddie Hung
Use a cell_cache to instantiate once rather than opt_me...
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2019-09-30
Eddie Hung
scc call on active module module only, plus cleanup
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2019-09-30
Eddie Hung
Use derived module
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2019-09-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-30
Eddie Hung
Update doc for equiv_opt
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2019-09-30
whitequark
Merge pull request #1406 from whitequark/connect_rpc
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2019-09-30
Eddie Hung
Merge pull request #1397 from btut/fix/python_wrappers_...
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2019-09-30
whitequark
rpc: new frontend.
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2019-09-30
whitequark
libs: import json11.
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2019-09-30
Miodrag Milanović
Merge pull request #1416 from YosysHQ/mmicko/frontend_b...
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2019-09-30
Clifford Wolf
Bump version
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2019-09-30
Clifford Wolf
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
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2019-09-30
Clifford Wolf
Merge pull request #1417 from YosysHQ/clifford/fixasync...
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2019-09-30
Clifford Wolf
Fix $dlatch handling in async2sync
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2019-09-30
Eddie Hung
Add latch test modified from #1363
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2019-09-30
Eddie Hung
Add LDCE/LDPE sim library, remove from *cells_xtra...
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2019-09-30
Marcin Kościelnicki
synth_xilinx: Support latches, remove used-up FF init...
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2019-09-30
Eddie Hung
Missing endmodule
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2019-09-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-30
Eddie Hung
Merge pull request #1414 from hzeller/improve-replace...
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2019-09-29
Eddie Hung
Merge pull request #1359 from YosysHQ/xc7dsp
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2019-09-29
Eddie Hung
FDCE_1 does not have IS_CLR_INVERTED
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2019-09-29
Eddie Hung
Fix "scc" call inside abc9 to consider all wires
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2019-09-29
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-29
Miodrag Milanovic
Fix reading aig files on windows
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2019-09-29
Miodrag Milanovic
Open aig frontend as binary file
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2019-09-29
Miodrag Milanović
Merge pull request #1413 from YosysHQ/mmicko/backend_bi...
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2019-09-29
Clifford Wolf
Merge pull request #1411 from aman-goel/YosysHQ-master
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2019-09-29
Henner Zeller
Avoid work in replace() if rules empty.
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2019-09-29
Eddie Hung
Big rework; flop info now mostly in cells_sim.v
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2019-09-28
Miodrag Milanovic
Add aiger and protobuf backends binary support
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2019-09-28
Miodrag Milanovic
Support binary files for backends, fixes #1407
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2019-09-28
Eddie Hung
Fix box name
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2019-09-28
Eddie Hung
Use abc_mergeability attr for "r" extension
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2019-09-28
Eddie Hung
Split ABC9 based on clocking only, add "abc_mergeabilit...
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2019-09-28
Eddie Hung
Fix infinite recursion
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2019-09-28
Eddie Hung
Add -select option to aigmap
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2019-09-28
Eddie Hung
Fix typo
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2019-09-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-27
Eddie Hung
Re-order
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2019-09-27
Eddie Hung
Missing (* mul2dsp *) for sliceB
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2019-09-27
Eddie Hung
equiv_opt to call async2sync when not -multiclock like...
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2019-09-27
Eddie Hung
Ooops AREG and BREG to default to -1
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2019-09-27
Aman Goel
Corrects btor2 backend
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2019-09-27
Marcin Kościelnicki
Fix _TECHMAP_REMOVEINIT_ handling.
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-27
Miodrag Milanović
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt...
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2019-09-27
Miodrag Milanovic
Change order of parameters, to work on other os
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2019-09-27
Clifford Wolf
Merge pull request #1404 from YosysHQ/fix_gzip_macos
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2019-09-26
Eddie Hung
Update doc with max cascade chain of 20
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2019-09-26
Eddie Hung
Do not always zero out C (e.g. during cascade breaks)
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2019-09-26
Eddie Hung
Update doc
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2019-09-26
Eddie Hung
Zero out ports
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2019-09-26
Eddie Hung
xilinx_dsp_cascade to also cascade AREG and BREG
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2019-09-26
Eddie Hung
Try recursive pmgen for P cascade
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2019-09-26
Eddie Hung
Missing an '&'
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2019-09-26
Eddie Hung
Combine 'flatten' & 'coarse' labels in synth_ecp5 so...
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2019-09-26
Miodrag Milanovic
Make read/write gzip files on macos works, fixes #1357
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2019-09-26
Eddie Hung
Typo
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2019-09-26
Eddie Hung
CREG to check for \keep
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2019-09-26
Eddie Hung
Remove newline
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2019-09-26
Eddie Hung
select once
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2019-09-26
Eddie Hung
Stop trying to be too smart by prematurely optimising
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