yosys.git
2019-01-17 Clifford WolfAdd "write_edif -gndvccy"
2019-01-15 Clifford WolfAdd optional nullstr argument to log_id()
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end
2019-01-15 Clifford WolfMerge pull request #788 from whitequark/master
2019-01-15 Clifford WolfMerge pull request #787 from whitequark/flowmap_relax
2019-01-14 whitequarkmanual: document some gates.
2019-01-14 whitequarkmanual: explain $tribuf cell.
2019-01-08 Clifford WolfImprove igloo2 example
2019-01-08 whitequarkflowmap: clean up terminology.
2019-01-08 whitequarkflowmap: implement depth relaxation.
2019-01-07 Clifford WolfFix typo in manual
2019-01-07 Clifford WolfBugfix in $memrd sharing
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-07 Clifford WolfSwitch "bugpoint" from system() to run_command()
2019-01-07 Clifford WolfMerge pull request #783 from whitequark/bugpoint
2019-01-07 whitequarkbugpoint: new pass.
2019-01-06 whitequarkflowmap: construct a max-volume max-flow min-cut, not...
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-06 Scott MansellRename cells based on the wires they drive.
2019-01-05 Clifford WolfAdd skeleton Yosys-Libero igloo2 example project
2019-01-05 Clifford WolfBugfix in Verilog string handling
2019-01-04 whitequarkflowmap: add -minlut option, to allow postprocessing...
2019-01-04 Clifford WolfMerge pull request #777 from mmicko/achronix_cell_sim_fix
2019-01-04 Miodrag MilanovicFix cells_sim.v for Achronix FPGA
2019-01-04 Clifford WolfRemove -m32 Verific eval lib build instructions
2019-01-04 Clifford WolfMerge pull request #776 from mmicko/unify_noflatten
2019-01-04 Clifford WolfUpdate Verific default path
2019-01-04 whitequarkflowmap: cleanup for clarity. NFCI.
2019-01-04 Miodrag MilanovicUnify usage of noflatten among architectures
2019-01-04 whitequarkflowmap: improve debug graph output. NFC.
2019-01-04 whitequarkflowmap: add link to longer version of paper. NFC.
2019-01-03 Clifford WolfMerge pull request #775 from whitequark/opt_flowmap
2019-01-03 whitequarkflowmap: new techmap pass.
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 whitequarkopt_expr: improve simplification of comparisons with...
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfImprove VerificImporter support for writes to asymmetri...
2019-01-02 Clifford WolfFix VerificImporter asymmetric memories error message
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2019-01-02 whitequarkopt_lut: reflect changes in sigmap.
2019-01-02 whitequarkopt_lut: use a worklist, and revisit cells affected...
2019-01-02 whitequarkopt_lut: count eliminated cells, and set opt.did_someth...
2019-01-02 whitequarksynth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 whitequarksynth: add k-LUT mode.
2019-01-02 whitequarksynth: improve script documentation. NFC.
2019-01-02 whitequarkcmp2lut: new techmap pass.
2019-01-02 whitequarkopt_expr: refactor simplification of unsigned X<onehot...
2019-01-02 whitequarkopt_expr: refactor simplification of signed X>=0 and...
2019-01-02 whitequarkopt_expr: simplify any unsigned comparisons with all...
2019-01-01 Clifford WolfMerge pull request #768 from whitequark/opt_lut_elim
2018-12-31 whitequarkopt_lut: eliminate LUTs evaluating to constants or...
2018-12-31 Clifford WolfFix handling of (* keep *) wires in wreduce
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-29 Larry DoolittleFix 7 instances of add_share_file to add_gen_share_file
2018-12-29 Larry DoolittleSquelch a little more trailing whitespace
2018-12-25 Icenowy Zhenganlogic: add latch cells
2018-12-23 Clifford WolfMerge pull request #761 from whitequark/proc_clean_partial
2018-12-23 Clifford WolfAdd "read_ilang -[no]overwrite"
2018-12-23 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-12-23 whitequarkproc_clean: remove any empty cases if all cases use...
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-22 whitequarkproc_clean: remove any empty cases at the end of the...
2018-12-21 whitequarkmanual: make description of $meminit ports match reality.
2018-12-21 Clifford WolfMerge pull request #758 from whitequark/tcl_script_args
2018-12-21 Clifford WolfMerge pull request #759 from whitequark/memory_collect_...
2018-12-21 whitequarkmemory_collect: do not truncate 'x from \INIT.
2018-12-20 whitequarkmanual: fix typos.
2018-12-20 whitequarktcl: add support for passing arguments to scripts.
2018-12-20 whitequarkmanual: document $meminit cell and memory_* passes.
2018-12-19 Icenowy Zhenganlogic: implement DRAM initialization
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix
2018-12-19 Icenowy Zhenganlogic: fix Makefile.inc
2018-12-19 Icenowy ZhengAnlogic: let LUT5/6 have more cost than LUT4-
2018-12-18 Clifford WolfMinor style fixes
2018-12-18 Clifford WolfMerge pull request #748 from makaimann/add-btor-ops
2018-12-18 Clifford WolfMerge pull request #751 from daveshah1/fix_589
2018-12-18 David Shahmemory_dff: Fix typo when checking init value
2018-12-18 Clifford WolfFix segfault in AST simplify
2018-12-18 Icenowy Zhenganlogic: set the init value of DFFs
2018-12-18 Icenowy ZhengAdd "dffinit -noreinit" parameter
2018-12-18 Clifford WolfImprove src tagging (using names and attrs) of cells...
2018-12-18 Icenowy ZhengAdd "dffinit -strinit high low"
2018-12-18 Icenowy Zhenganlogic: fix dbits of Anlogic Eagle DRAM16X4
2018-12-17 makaimannAdd btor ops for $mul, $div, $mod and $concat
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec
2018-12-17 Clifford WolfMerge pull request #744 from whitequark/write_verilog_...
2018-12-17 Icenowy Zhenganlogic: add support for Eagle Distributed RAM
2018-12-17 Icenowy ZhengRevert "Leave only real black box cells"
2018-12-16 Clifford WolfMerge pull request #745 from YosysHQ/revert-714-abc_pre...
2018-12-16 Clifford WolfRevert "Proof-of-concept: preserve naming through ABC...
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