yosys.git
2015-02-12 Clifford WolfAdded "proc_dlatch"
2015-02-10 Clifford WolfLess aggressive "share" defaults
2015-02-10 Clifford WolfImproved read_verilog support for empty behavioral...
2015-02-10 Clifford WolfAdded "scc -expect <N> -nofeedback"
2015-02-09 Clifford WolfSome hashlib improvements
2015-02-09 Clifford WolfVarious changes to release checklist
2015-02-09 Clifford WolfFixed creation of command reference in manual
2015-02-09 Clifford WolfWe are now in 0.5+ development
2015-02-09 Clifford WolfYosys 0.5 yosys-0.5
2015-02-09 Clifford WolfBugfix in "make vcxsrc"
2015-02-09 Clifford WolfUpdated command reference in manual
2015-02-09 Clifford WolfVarious presentation fixes
2015-02-08 Clifford WolfFixed iterator invalidation bug in "rename" command
2015-02-08 Clifford WolfCodingReadme update
2015-02-08 Clifford WolfFixed bug in "show -format .."
2015-02-08 Clifford WolfAdded new APIs to changelog
2015-02-08 Clifford WolfFixed eval_select_op() api
2015-02-08 Clifford WolfAdded eval_select_args() and eval_select_op()
2015-02-08 Clifford WolfMinor "make vgtest" changes
2015-02-08 Clifford WolfVarious ModIndex improvements
2015-02-08 Clifford WolfAdded Yosys 0.5 Changelog
2015-02-08 Clifford WolfVarious updates to CodingReadme
2015-02-08 Clifford WolfAdded equiv_add
2015-02-07 Clifford WolfIgnore explicit assignments to constants in HDL code
2015-02-07 Clifford WolfFixed a bug with autowire bit size
2015-02-07 Clifford Wolffixed typo
2015-02-07 Clifford WolfAdded "yosys-config --build modname.so cppsources.."
2015-02-07 Clifford WolfAdded SigSpec::has_const()
2015-02-07 Clifford WolfCleanup in add_share_file make macro
2015-02-07 Clifford WolfRemoved "make mklibyosys"
2015-02-07 Clifford WolfImproved building of plugins
2015-02-07 Clifford WolfAdded "make uninstall"
2015-02-07 Clifford WolfAdded cell->known(), cell->input(portname), cell->outpu...
2015-02-06 Clifford WolfAdded "select -read"
2015-02-05 Clifford WolfAuto-detect TCL version
2015-02-04 Clifford WolfAdded onehot attribute
2015-02-04 Clifford WolfFixed opt_clean performance bug
2015-02-04 Clifford WolfDisabled (unused) Xilinx tristate buffers
2015-02-03 Clifford WolfUsing design->selected_modules() in opt_*
2015-02-03 Clifford WolfSkip blackbox modules in design->selected_modules()
2015-02-03 Clifford WolfAdded "yosys -L logfile"
2015-02-01 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-02-01 Clifford Wolfno support for 6-series xilinx devices
2015-02-01 Clifford WolfMerge pull request #48 from rubund/master
2015-02-01 Clifford WolfImproved performance in equiv_simple
2015-02-01 Ruben UndheimFixed typos found by lintian
2015-02-01 Clifford WolfRemoved old XST-based xilinx examples
2015-02-01 Clifford WolfAdded Xilinx example for Basys3 board
2015-02-01 Clifford WolfAdded EDIF backend support for multi-bit cell ports
2015-02-01 Clifford WolfAdded missing ports and parameters to xilinx brams
2015-02-01 Clifford WolfAdded "make mklibyosys", some minor API changes
2015-01-31 Clifford WolfMinor README changes
2015-01-31 Clifford WolfRemoved TODO list from README file
2015-01-31 Clifford WolfAdded yosys_banner(), Updated Copyright range
2015-01-31 Clifford WolfAdded <algorithm> include to hashlib.h
2015-01-31 Clifford WolfUsing selections in "ls" command
2015-01-31 Clifford WolfShorter "dump" options
2015-01-31 Clifford WolfBugfix in opt_const $eq -> buffer code
2015-01-31 Clifford WolfLog msg change
2015-01-31 Clifford WolfFixed equiv_make for partially undriven nets (e.g....
2015-01-31 Clifford WolfAdded "equiv_induct -undef"
2015-01-31 Clifford WolfAdded "equiv_simple -undef"
2015-01-31 Clifford WolfAdded "equiv_make -blacklist <file> -encfile <file>"
2015-01-30 Clifford WolfSynced RTLIL::unescape_id() to log_id() behavior
2015-01-30 Clifford WolfAdded "fsm -encfile"
2015-01-30 Clifford WolfMore log_id() stuff
2015-01-30 Clifford WolfSome cleanups in log.cc
2015-01-27 Clifford WolfImproved an error message
2015-01-27 Clifford WolfFixed bug in equiv_miter
2015-01-27 Clifford WolfAdded "sat -show-ports"
2015-01-27 Clifford WolfBugfix in resource sharing test
2015-01-27 Clifford WolfUpdaed ABC to hg rev 61ad5f908c03
2015-01-25 Clifford WolfRethrow with "catch(...) throw;"
2015-01-25 Clifford WolfAdded equiv_remove
2015-01-25 Clifford WolfAdded equiv_miter
2015-01-24 Clifford WolfAdded ENABLE_NDEBUG makefile options
2015-01-24 Clifford WolfAdded #ifdef NDEBUG for log_assert()
2015-01-24 Clifford WolfFixed xilinx FDSE sim model
2015-01-23 Clifford WolfVarious equiv_* improvements
2015-01-23 Clifford WolfAdded dict/pool.sort()
2015-01-22 Clifford WolfImprovements in equiv_make, equiv_induct
2015-01-22 Clifford WolfImproved xdot calling
2015-01-22 Clifford WolfAdded equiv_induct
2015-01-22 Clifford WolfVarious equiv_simple improvements
2015-01-22 Clifford WolfMoved equiv stuff to passes/equiv/
2015-01-21 Clifford WolfProgress in equiv_simple
2015-01-21 Clifford WolfFixed opt_muxtree performance bug
2015-01-20 Clifford WolfFaster "make clean-abc"
2015-01-20 Clifford WolfREADME stuff
2015-01-19 Clifford WolfAdded equiv_simple
2015-01-19 Clifford WolfAdded equiv_status
2015-01-19 Clifford WolfAdded equiv_make command
2015-01-19 Clifford WolfAdded $equiv cell type
2015-01-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-01-18 Clifford WolfVarious cleanups in xilinx techlib
2015-01-18 Clifford WolfRefactoring of memory_bram and xilinx brams
2015-01-18 Clifford WolfMerge pull request #47 from mschmoelzer/master
2015-01-18 Martin SchmölzerAdd "echo-yosys-ver" and "echo-git-rev" Makefile targets.
2015-01-18 Clifford Wolfimprovements in muxtree/select_leaves test
2015-01-18 Clifford WolfImprovements in opt_muxtree
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