yosys.git
2014-07-28 Clifford WolfFixed RTLIL code generator for part select of parameter
2014-07-28 Clifford WolfFixed width detection for part selects
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and...
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-28 Clifford WolfAdded std::initializer_list<> constructor to SigSpec
2014-07-28 Clifford WolfAdded cover() to all SigSpec constructors
2014-07-28 Clifford WolfFixed signdness detection of expressions with bit-...
2014-07-28 Clifford WolfImprovements in tests/vloghtb
2014-07-27 Clifford WolfAdded techmap -extern
2014-07-27 Clifford WolfAdded proper Design->addModule interface
2014-07-27 Clifford WolfAdded topological sorting to techmap
2014-07-27 Clifford WolfAdded SigPool::check(bit)
2014-07-27 Clifford WolfSmall improvements in PerformanceTimer API
2014-07-27 Clifford WolfFixed bug in opt_clean
2014-07-27 Clifford WolfImproved performance of opt_const on large modules
2014-07-27 Clifford WolfAdded RTLIL::SigSpec::remove_const() handling of packed...
2014-07-27 Clifford WolfAdded RTLIL::SigSpecConstIterator
2014-07-27 Clifford WolfFixed a bug in opt_clean and some RTLIL API usage cleanups
2014-07-27 Clifford WolfAdded log_cmd_error_expection
2014-07-27 Clifford WolfFixed verific bindings for new RTLIL api
2014-07-27 Clifford WolfFixed ilang parser for new RTLIL API
2014-07-27 Clifford WolfUsing new obj iterator API in a few places
2014-07-27 Clifford WolfAdded RTLIL::Module::wire(id) and cell(id) lookup functions
2014-07-27 Clifford WolfAdded RTLIL::Design::modules()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 Clifford WolfAdded conversion from ObjRange to std::vector and std...
2014-07-27 Clifford WolfAdded RTLIL::ObjIterator and RTLIL::ObjRange
2014-07-27 Clifford WolfUsing std::move() in SigSpec move constructor
2014-07-27 Clifford WolfAdded RTLIL::SigSpec move constructor and move assignme...
2014-07-27 Clifford WolfMostly cosmetic changes to rtlil.h
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfNew message for completion of build
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfAdded tests/various/.gitignore
2014-07-26 Clifford WolfAdded tests/various/submod_extract.ys
2014-07-26 Clifford WolfAdded support for here documents
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname)
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfAdded some missing "const" in rtlil.h
2014-07-26 Clifford WolfAdded RTLIL::Module::connections()
2014-07-26 Clifford WolfAdded RTLIL::Module::connect(const RTLIL::SigSig&)
2014-07-26 Clifford WolfUse "wget -N" in tests/vloghtb/run-test.sh
2014-07-26 Clifford WolfAdded "passed" message to make test targets
2014-07-26 Clifford WolfAutomatically pack SigSpec on copy/assign
2014-07-26 Clifford WolfAdded new RTLIL::Cell port access methods
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 Clifford WolfCosmetic fixes for "make abc"
2014-07-26 Clifford WolfAdded "Checklist for adding internal cell types"
2014-07-25 Clifford WolfAdded copy-constructor-like module->addCell(name, other...
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-25 Clifford WolfVarious RTLIL::SigSpec related code cleanups
2014-07-25 Clifford WolfAdded RTLIL::SigSpec is_chunk()/as_chunk() API
2014-07-25 Clifford WolfAdded "make vgtest"
2014-07-25 Clifford WolfFixed two memory leaks in ast simplify
2014-07-25 Clifford WolfRenamed some of the test cases in tests/simple to avoid...
2014-07-25 Clifford WolfFixed memory corruption in "opt_reduce" pass
2014-07-25 Clifford WolfDisabled cover() for non-linux builds
2014-07-25 Clifford WolfAdded more stuff to checklist
2014-07-25 Clifford WolfUpdated verific build/test instructions
2014-07-25 Clifford WolfImprovements in "cover" command
2014-07-25 Clifford WolfRemoved Minisat dependency on zlib
2014-07-25 Clifford WolfAdded more stuff to the checklist
2014-07-25 Clifford WolfFixed typo in cover id
2014-07-25 Clifford WolfAdded "make clean-abc"
2014-07-25 Clifford WolfFurther improved "make" prettiness
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns
2014-07-24 Clifford WolfUpdated ABC to hg id "b1e63d18768d"
2014-07-24 Clifford WolfAdded cover() calls to opt_const
2014-07-24 Clifford WolfAdded cover_list() API
2014-07-24 Clifford WolfAdded "make SMALL=1"
2014-07-24 Clifford WolfNow "make PRETTY=1" is the default setting
2014-07-24 Clifford WolfAdded percentage display to "make PRETTY=1"
2014-07-24 Clifford WolfAdded "make PRETTY=1"
2014-07-24 Clifford WolfAdded "cover" command
2014-07-24 Clifford WolfSome improvements in SigSpec packing/unpacking and...
2014-07-24 Clifford WolfNow using a dedicated ELF section for all coverage...
2014-07-24 Clifford WolfSmall changes regarding cover() and check() in SigSpec
2014-07-24 Clifford WolfRenamed RELEASE_CHECKLIST -> CHECKLIST
2014-07-24 Clifford WolfAdded support for YOSYS_COVER_FILE env variable
2014-07-24 Clifford WolfAdded cover() calls to RTLIL::SigSpec methods
2014-07-24 Clifford WolfAdded support for YOSYS_COVER_DIR env variable
2014-07-24 Clifford WolfAdded cover() API
2014-07-24 Clifford WolfAdded RELEASE_CHECKLIST
2014-07-24 Clifford WolfAdded "make config-gcc-4.7"
2014-07-24 Clifford WolfAdded "make vloghtb"
2014-07-23 Clifford WolfAdded hashing to RTLIL::SigSpec relational and equal...
2014-07-23 Clifford WolfDisabled RTLIL::SigSpec::check() in release builds
2014-07-23 Clifford WolfFixed release build
2014-07-23 Clifford WolfVarious fixes in Verific frontend for new RTLIL API
2014-07-23 Clifford WolfAdded RTLIL::SigSpec::repeat()
2014-07-23 Clifford WolfVarious small fixes (from gcc compiler warnings)
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfTurned RTLIL::SigSpec::optimize() to a no-op: a packed...
2014-07-23 Clifford WolfFixed manual/CHAPTER_Prog/stubnets.cc
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