gem5.git
2012-05-10 Ali Saidigem5: assert before indexing intro arrays to verify...
2012-05-10 Ali Saidigem5: fix some iterator use and erase bugs
2012-05-10 Ali Saidigem5: fix a number of use after free issues
2012-05-10 Ali Saidibase: fix a invalid ?: operator
2012-05-10 Ali Saidigem5: Fix a number of incorrect case statements
2012-05-10 Ali SaidiARM: Update m5op assembly for thumb compilation.
2012-05-10 Ali Saidistats: track if the stats have been enabled and prevent...
2012-05-10 Ali SaidiCache: Panic if you attempt to create a checkpoint...
2012-05-10 Pritha GhoshalIGbE: Fix writeback conditions for i8254x GbE in update...
2012-05-09 Nathan Binkertstats: update stats for no_value -> nan
2012-05-09 Nathan Binkertstats: use nan instead of no_value
2012-05-09 Andreas HanssonMEM: Add the communication monitor
2012-05-08 Steve Reinhardtscons: allow override of SWIG binary on command line
2012-05-08 Andreas HanssonMEM: Do not forward uncacheable to bus snoopers
2012-05-04 Andreas HanssonRuby: Ensure snoop requests are sent using sendTimingSn...
2012-05-04 Nilay VaishRegression: Move x86 fs ruby simulation from quick...
2012-05-03 Jayneel GandhiConfig: Fix help msg for option --mem-size
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-30 Nilay VaishRegression: Stats update for X86 Ruby FS test
2012-04-29 Gabe BlackX86: Fix the IMUL_R_P_I macroop.
2012-04-29 Vince WeaverX86: Fix up the open system call's flags.
2012-04-29 Vince WeaverX86: Make gem5 ignore a bunch of syscalls.
2012-04-28 Nilay VaishGarnet: Correct computation of link utilization
2012-04-27 Nilay Vaishutil/regress: Add the missing comma in the list of...
2012-04-26 Nilay VaishRegression: Add a test for x86 timing full system ruby...
2012-04-25 Nilay VaishRuby: Remove extra statements from Sequencer
2012-04-25 Andreas HanssonMEM: Use base class Master/SlavePort pointers in the bus
2012-04-25 Andreas HanssonMEM: Add the PortId type and a corresponding id field...
2012-04-25 Andreas Hanssonclang/gcc: Use STL hash function for int64_t and uint64_t
2012-04-24 Gabe BlackX86: Update stats for the slightly changed TLB behavior.
2012-04-24 Gabe BlackX86: Clear out duplicate TLB entries when adding a...
2012-04-23 Gabe BlackISA: Put parser generated files in a "generated" directory.
2012-04-23 Steve Reinhardtscons: update minimum SWIG version to 1.3.34
2012-04-22 Gabe Blackbase: Include cassert in trie.hh.
2012-04-21 Gabe BlackX86: Report an error if there's no kernel object, don...
2012-04-17 Jayneel GandhiSE Config: Changed se.py to support multithreaded mode
2012-04-16 Jayneel GandhiConfig: Add command line options for disk image and...
2012-04-15 Gabe BlackCPU: Tidy up some formatting and a DPRINTF in the simpl...
2012-04-15 Gabe BlackX86: Fix a tiny typo in the load/store microop constructor.
2012-04-15 Gabe BlackX86: Use the AddrTrie class to implement the TLB.
2012-04-15 Gabe Blacksim: Update some comments in trie.hh that were meant...
2012-04-15 Gabe Blacksim: A trie data structure specifically to speed up...
2012-04-14 Andreas HanssonRuby: Use MasterPort base-class pointers where possible
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-04-14 Andreas HanssonRegression: Add ANSI colours to highlight test status
2012-04-14 Andreas Hanssonclang/gcc: Fix compilation issues with clang 3.0 and...
2012-04-13 Steve ReinhardtSCons: restore Werror option in src/SConscript
2012-04-12 Andreas HanssonStats: Update with use of std::map for ordered iteratio...
2012-04-12 Andreas HanssonRuby: Ensure order-dependent iteration uses an ordered map
2012-04-10 Gabe Blacktests: Fix building unit tests.
2012-04-07 Brad Beckmannrubytest: remove spurious printf
2012-04-06 Brad Beckmannregress: ruby random tester and hammer stats updates
2012-04-06 Brad Beckmannruby: set SimpleTiming as the default cpu
2012-04-06 Lisa Hsuslicc: Controllers attached to Sequencers no longer...
2012-04-06 Brad Beckmannsim-ruby: checkpointing fixes and dependent eventq...
2012-04-06 Brad Beckmannslicc: fixed error message when the type has no inheritance
2012-04-06 Brad BeckmannMOESI_hammer: tbe allocation and dependent wakeup fixes
2012-04-06 Brad Beckmannpython: added __nonzero__ function to SimObject Bool...
2012-04-06 Brad BeckmannMOESI_hammer: fixed bug with single cpu + flushes,...
2012-04-06 Brad Beckmannrubytest: seperated read and write ports.
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-04-05 Tushar KrishnaNetworkTest: remove unnecessary memory allocation
2012-04-05 Nilay VaishConfig: corrects the way Ruby attaches to the DMA ports
2012-04-05 Andreas HanssonRuby: Fix the example configurations option parsing
2012-04-05 Andreas HanssonPython: Make the All proxy traverse SimObject children...
2012-04-03 Andreas HanssonAtomic: Remove the physmem_port and access memory directly
2012-03-31 Gabe BlackX86: Fix address size handling so real mode works properly.
2012-03-30 Andreas HanssonMEM: Remove legacy DRAM in preparation for memory updates
2012-03-30 Andreas HanssonRuby: Remove the physMemPort and instead access memory...
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-30 Andreas HanssonCPU: Unify initMemProxies across CPUs and simulation...
2012-03-28 Nilay VaishConfig: Change the way options are added
2012-03-27 Nilay VaishConfig: Move setWorkCountOptions() to Simulation.py
2012-03-26 Andreas Hanssonrange_map: Enable const find and iteration
2012-03-26 Andreas HanssonPower: Change bitfield name to avoid conflicts with...
2012-03-23 Andreas HanssonRuby: Fix Set::print for 32-bit hosts
2012-03-22 Andreas HanssonMEM: Unify bus access methods and prepare for master...
2012-03-22 Andreas HanssonMEM: Split SimpleTimingPort into PacketQueue and ports
2012-03-22 Andreas HanssonScons: Remove Werror=False in SConscript files
2012-03-21 Andreas HanssonPython: Fix a conditional expression that requires...
2012-03-21 Ali SaidiARM: Update stats for IT and conditional branch changes
2012-03-21 Nathanael PremillieuARM: Fix case where cond/uncond control is mis-specified
2012-03-21 Ali SaidiARM: Clean up condCodes in IT blocks.
2012-03-21 Geoffrey BlakeARM: IT doesn't need to be serializing.
2012-03-21 Andrew LukefahrO3: Fix sizing of decode to rename skid buffer.
2012-03-21 Koan-Sin TanARM: Add RTC to PBX System
2012-03-21 Brian GraysonO3: Fix size of skid buffer between fetch and decode...
2012-03-21 Ali SaidiARM: Fix uninitialized value in ARM RTC model.
2012-03-19 Tushar KrishnaGarnet: Stats at vnet granularity + code cleanup
2012-03-19 Andreas Hanssongcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 Andreas Hanssonclang: Fix recently introduced clang compilation errors
2012-03-19 Andreas Hanssonscripts: Fix to ensure that port connection count is...
2012-03-16 Nilay Vaishruby_fs.py: Add call to createInterruptController()
2012-03-16 Nilay VaishFSConfig.py: fix a typo makeLinuxAlphaRubySystem
2012-03-16 Marc Orrbuild: remove implicit-cache setting of scons from...
2012-03-11 Nilay Vaishse.py: Changes to ruby portion due to SE/FS merge
2012-03-11 Brian GraysonO3: Add fatal when fetchWidth > Impl::MaxWidth.
2012-03-09 Ali SaidiARM: Fix memory starting at non-zero address and exceed...
2012-03-09 Ali SaidiARM: Update stats for CBNZ fix.
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