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litex.git
2013-03-26
Sebastien Bourdeauducq
fhdl/specials: clean up clock domain handling
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2013-03-25
Sebastien Bourdeauducq
actorlib/structuring/Cast: support inversion
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2013-03-25
Sebastien Bourdeauducq
bank/csrgen/BankArray: retain name information
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2013-03-25
Sebastien Bourdeauducq
bank/description/Register: add get_size
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2013-03-23
Sebastien Bourdeauducq
genlib/record: use getattr instead of __dict__
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2013-03-23
Sebastien Bourdeauducq
genlib/record: add eq
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2013-03-22
Sebastien Bourdeauducq
genlib/fifo: simple synchronous FIFO
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2013-03-22
Sebastien Bourdeauducq
fhdl/module: support clock domain remapping of submodules
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2013-03-21
Sebastien Bourdeauducq
genlib/cdc/MultiReg: output clock domain defaults to sys
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2013-03-19
Sebastien Bourdeauducq
examples/sim/fir: convert to new API
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2013-03-18
Sebastien Bourdeauducq
fhdl/verilog: optionally disable clock domain creation
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2013-03-18
Sebastien Bourdeauducq
examples/basic/arrays: demonstrate lowering of Array...
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2013-03-18
Sebastien Bourdeauducq
Lowering of Special expressions + support ClockSignal...
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2013-03-18
Sebastien Bourdeauducq
fhdl/tools/_ArrayLowerer: complete support for arrays...
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2013-03-18
Sebastien Bourdeauducq
fhdl/tools/value_bits_sign: support not
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2013-03-17
Sebastien Bourdeauducq
fhdl/structure: style fix
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2013-03-17
Sébastien Bourdeauducq
Merge pull request #6 from larsclausen/master
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2013-03-15
Sebastien Bourdeauducq
genlib/cdc/MultiReg: implement rename_clock_domain...
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2013-03-15
Sebastien Bourdeauducq
genlib/cdc/MultiReg: remove idomain
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2013-03-15
Sebastien Bourdeauducq
fhdl/specials: fix rename_clock_domain declarations
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2013-03-15
Sebastien Bourdeauducq
sim: remove PureSimulable (superseded by Module)
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2013-03-15
Sebastien Bourdeauducq
structure: remove Fragment.call_sim
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2013-03-15
Sebastien Bourdeauducq
sim: compatibility with new ClockDomain API
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2013-03-15
Sebastien Bourdeauducq
Local clock domain example
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2013-03-15
Sebastien Bourdeauducq
Make ClockDomains part of fragments
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2013-03-14
Sebastien Bourdeauducq
flow/actor/filter_endpoints: deterministic order
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2013-03-13
Sebastien Bourdeauducq
bank/csrgen/BankArray: create banks in sorted order
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2013-03-13
Sebastien Bourdeauducq
bank/description: modify reg/mem in-place
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2013-03-12
Lars-Peter...
Allow SimActors to produce/consume a constant stream...
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2013-03-12
Lars-Peter...
Add support for negative slice indices
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2013-03-12
Sebastien Bourdeauducq
examples/pytholite: use new APIs
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2013-03-12
Sebastien Bourdeauducq
sim/generic: support implicit get_fragment
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2013-03-12
Sebastien Bourdeauducq
vpi: make it work by default on Arch
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2013-03-12
Sebastien Bourdeauducq
examples/basic: use new APIs
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2013-03-12
Sebastien Bourdeauducq
fhdl/verilog: implicit get_fragment
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2013-03-12
Sebastien Bourdeauducq
fhdl/specials/Memory: automatic name#
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2013-03-12
Sebastien Bourdeauducq
bank: automatic register naming
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2013-03-12
Sebastien Bourdeauducq
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
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2013-03-12
Sebastien Bourdeauducq
fhdl/tracer: recognize LOAD_DEREF opcode
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2013-03-11
Sebastien Bourdeauducq
fhdl/tracer: remove leading underscores from names
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2013-03-11
Sebastien Bourdeauducq
README: update
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2013-03-11
Sebastien Bourdeauducq
bus/asmibus: use implicit finalization
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2013-03-10
Sebastien Bourdeauducq
Fix Register name conflict between Pytholite and Bank
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2013-03-10
Sebastien Bourdeauducq
bank/eventmanager: use module and autoreg
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2013-03-10
Sebastien Bourdeauducq
bus/asmibus: use fhdl.module API
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2013-03-10
Sebastien Bourdeauducq
fhdl/module: replace autofragment
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2013-03-10
Sebastien Bourdeauducq
bank/description/AutoReg: check that get_memories and...
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2013-03-09
Sebastien Bourdeauducq
bank/csrgen: BankArray
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2013-03-09
Sebastien Bourdeauducq
bank/description: AutoReg
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2013-03-09
Sebastien Bourdeauducq
migen/fhdl/autofragment: factorize
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2013-03-09
Sebastien Bourdeauducq
fhdl/autofragment: remove legacy functions
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2013-03-09
Sebastien Bourdeauducq
fhdl/tools/flat_iteration: generalize
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2013-03-09
Sebastien Bourdeauducq
fhdl/autofragment: fix submodules
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2013-03-09
Sebastien Bourdeauducq
fhdl/autofragment: empty build_fragment by default
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2013-03-09
Sebastien Bourdeauducq
Use common definition for FinalizeError
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2013-03-08
Sebastien Bourdeauducq
csr/SRAM: support for writes with memory widths larger...
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2013-03-06
Sebastien Bourdeauducq
fhdl/verilog: tristate outputs are always wire
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2013-03-03
Sebastien Bourdeauducq
bus/csr: support memories with larger word width than...
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2013-03-03
Sebastien Bourdeauducq
fhdl/autofragment: bugfixes + add auto_attr
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2013-03-02
Sebastien Bourdeauducq
fhdl/autofragment: FModule
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2013-03-01
Sebastien Bourdeauducq
csr/SRAM: prefix page register with memory name
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2013-02-27
Sebastien Bourdeauducq
fhdl/verilog: insert reset before listing signals
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2013-02-25
Sebastien Bourdeauducq
bank/description: memprefix
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2013-02-25
Sebastien Bourdeauducq
fhdl/specials: allow setting memory name
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2013-02-25
Sebastien Bourdeauducq
uio/ioo: fix specials
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2013-02-24
Sebastien Bourdeauducq
fhdl/specials/Instance: _printintbool -> verilog_printexpr
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2013-02-23
Sebastien Bourdeauducq
examples/psync: cleanup
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2013-02-23
Sebastien Bourdeauducq
examples/basic/psync: demonstrate the new features
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2013-02-23
Sebastien Bourdeauducq
genlib: clock domain crossing elements
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2013-02-23
Sebastien Bourdeauducq
fhdl/verilog: support special lowering and overrides
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2013-02-22
Sebastien Bourdeauducq
examples/fir: better filter
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2013-02-22
Sebastien Bourdeauducq
corelogic -> genlib
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2013-02-22
Sebastien Bourdeauducq
fhdl: inline synthesis directive support
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2013-02-22
Sebastien Bourdeauducq
doc: new 'specials' API
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2013-02-22
Sebastien Bourdeauducq
New 'specials' API
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2013-02-19
Sebastien Bourdeauducq
doc: tristates
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2013-02-19
Sebastien Bourdeauducq
fhdl: TSTriple
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2013-02-14
Sebastien Bourdeauducq
fhdl: tristate support
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2013-02-11
Sebastien Bourdeauducq
fhdl/autofragment: from_attributes
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2013-02-10
Sebastien Bourdeauducq
doc: fix signal desc layout
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2013-02-10
Sebastien Bourdeauducq
Merge branch 'master' of github.com:milkymist/migen
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2013-02-10
Sebastien Bourdeauducq
doc/dataflow: remove ActorNode
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2013-02-10
Sebastien Bourdeauducq
doc/dataflow: remove ALA
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2013-02-10
Sebastien Bourdeauducq
doc: multiple clock domains
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2013-02-10
Sebastien Bourdeauducq
doc: do not inline examples as this never works with...
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2013-02-10
Sebastien Bourdeauducq
doc: update to new Migen APIs
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2013-02-09
Sebastien Bourdeauducq
sim: default runner to Icarus Verilog
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2013-02-09
Sebastien Bourdeauducq
flow/perftools: finish removing ActorNode
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2013-01-24
Sebastien Bourdeauducq
fhdl/structure: store clock domain name
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2013-01-23
Sebastien Bourdeauducq
fhdl/verilog: fix spurious clock/reset signals on multi...
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2013-01-05
Sebastien Bourdeauducq
corelogic: complex arithmetic support
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2013-01-05
Sebastien Bourdeauducq
fhdl: support nested statement lists
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2012-12-19
Sebastien Bourdeauducq
pytholite: fix bug with constant assignment to register
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2012-12-19
Sebastien Bourdeauducq
pytholite: prune unused registers
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2012-12-18
Sebastien Bourdeauducq
Do not use super()
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2012-12-16
Sebastien Bourdeauducq
examples/pytholite: fix imports
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2012-12-14
Sebastien Bourdeauducq
fhdl/tools: bitreverse
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2012-12-14
Sebastien Bourdeauducq
actorlib/sim/SimActor: do not drive busy low when gener...
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2012-12-14
Sebastien Bourdeauducq
Token: support idle_wait
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2012-12-14
Sebastien Bourdeauducq
Move Token to migen.flow.transactions
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