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yosys.git
2013-11-04
Martin Schmölzer
Allow setting of installation destination via DESTDIR...
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2013-11-04
Clifford Wolf
Improved comments on topological sort in edif backend
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2013-11-04
Clifford Wolf
Fixes for early width and sign detection in ast simplifier
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2013-11-04
Clifford Wolf
further improved early width and sign detection in...
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2013-11-03
Clifford Wolf
Added simple topological sort to edif backend
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2013-11-03
Clifford Wolf
Write yosys version to output files
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2013-11-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-11-03
Clifford Wolf
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
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2013-11-03
Clifford Wolf
Added resolution of positional arguments to hierarchy...
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2013-11-03
Clifford Wolf
Ignore explicit unconnected ports in intersynth backend
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2013-11-02
Clifford Wolf
Behavior should be identical now to rev. 0b4a64ac6adbd6...
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2013-11-02
Clifford Wolf
Added roadmap to readme file
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2013-11-02
Clifford Wolf
Various ast changes for early expression width detectio...
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2013-10-31
Clifford Wolf
Added DFFSR cell to techlibs/cmos/cmos_cells.lib
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2013-10-31
Clifford Wolf
Added placeholder check to dfflibmap and cleaned up...
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2013-10-31
Clifford Wolf
Changed MiniSAT feater defines again
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2013-10-31
Clifford Wolf
Added paragraph to README file to avoid mycells.lib...
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2013-10-31
Clifford Wolf
README file typo fix
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2013-10-31
Clifford Wolf
Some additions to the README file
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2013-10-30
Clifford Wolf
Fixed ezminisat C++ errors: undef PRIi64
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2013-10-29
Clifford Wolf
Added detection for endless recursion in fsm_detect...
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2013-10-29
Clifford Wolf
Fixed help message typo (memory pass)
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2013-10-29
Clifford Wolf
Added -format option to splitnets
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2013-10-27
Clifford Wolf
Merge pull request #12 from jameswalmsley/master
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2013-10-27
James Walmsley
[EXAMPLES] Ported the mojo counter example to Zynq...
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2013-10-27
Clifford Wolf
Fixed get_share_file_name() for installed yosys
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2013-10-27
Clifford Wolf
Cleanups in xilinx examples
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2013-10-27
Clifford Wolf
Added synth_xilinx command
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2013-10-27
Clifford Wolf
Added API and Makefile rules for share/ files
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2013-10-27
Clifford Wolf
Added design->full_selection() helper method
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2013-10-27
Clifford Wolf
Moved simple xilinx counter sim example to subdir
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2013-10-27
Clifford Wolf
Xilinx mojo_counter example is now working
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2013-10-27
Clifford Wolf
Fixed hex string generation bug in edif backend
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2013-10-26
Clifford Wolf
Renamed techlibs/xilinx7 to techlibs/xilinx
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2013-10-26
Clifford Wolf
Improved xilinx mojo_counter example
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2013-10-26
Clifford Wolf
Added support for i/o buffers to iopadmap
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2013-10-26
Clifford Wolf
Added another xilinx example (not funcional yet)
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2013-10-24
Clifford Wolf
Added support for sr flip-flops to dfflibmap
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2013-10-24
Clifford Wolf
Added support for complex set-reset flip-flops in proc_dff
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (passes)
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (backends)
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (frontends)
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2013-10-24
Clifford Wolf
Fixed handling of boolean attributes (kernel)
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2013-10-23
Clifford Wolf
Fixed parsing of value-less attributes in ilang
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2013-10-21
Clifford Wolf
Improved handling of dff with async resets
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2013-10-18
Clifford Wolf
Added handling of multiple async paths in proc_arst
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2013-10-18
Clifford Wolf
Changed NEW_WIRE API to return the wire, not the signal
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2013-10-18
Clifford Wolf
Added dffsr support to proc_dff pass
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2013-10-18
Clifford Wolf
Added RTLIL NEW_WIRE macro
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2013-10-18
Clifford Wolf
Bugfix in dffsr techmap rules
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2013-10-18
Clifford Wolf
Added techmap rules for $sr, $dffsr and $dlatch
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2013-10-18
Clifford Wolf
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
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2013-10-18
Clifford Wolf
Added $sr, $dffsr and $dlatch cell types
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2013-10-17
Clifford Wolf
Improved way of connecting ports in techmap pass
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2013-10-17
Clifford Wolf
Only prefer connected signals iff they have public...
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2013-10-17
Clifford Wolf
Added -buf, -true and -false options to blif backend
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2013-10-17
Clifford Wolf
Fixed bug in synthesis of memories that are never written
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2013-10-17
Clifford Wolf
Avoid re-arranging signals on register outputs
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2013-10-17
Clifford Wolf
Fixed detection of major wires in opt_clean
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2013-10-16
Clifford Wolf
Added iopadmap pass
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2013-10-16
Clifford Wolf
Moved dfflibmap from passes/dfflibmap to passes/techmap
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2013-10-16
Clifford Wolf
Added map, par and bitgen to xlinx7 example
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2013-10-16
Clifford Wolf
Fixed parsing or liberty file statements such as 'clock...
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2013-10-11
Clifford Wolf
Added recommended apt-get commands to README
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2013-10-11
Clifford Wolf
Fixed minisat include
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2013-10-03
Clifford Wolf
Pinned ABC revision to 0f9e5488ced3
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2013-09-17
Clifford Wolf
Improvements in EDIF backend
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2013-09-15
Clifford Wolf
Added additional options to BLIF backend
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2013-09-15
Clifford Wolf
Added BLIF backend
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2013-09-15
Clifford Wolf
A couple of small fixes in SPICE backend
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2013-09-15
Clifford Wolf
Moved common techlib files to techlibs/common
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2013-09-15
Clifford Wolf
Updated manual
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2013-09-14
Clifford Wolf
Added spice testbench to techlibs/cmos
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2013-09-14
Clifford Wolf
Added spice backend
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2013-09-03
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-09-03
Clifford Wolf
Added -selected option to various backends
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2013-08-28
Clifford Wolf
Encode large (>32 bits) parameters as hex string in...
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2013-08-27
Clifford Wolf
Improved edif backend
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2013-08-27
Clifford Wolf
Added mapping to techlibs/xilinx7 testbench (exposes...
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2013-08-22
Clifford Wolf
Added simple xilinx7 technology mapping files
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2013-08-22
Clifford Wolf
More explicit integer output in verilog backend
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2013-08-22
Clifford Wolf
Added correct encoding of identifiers in EDIF backend
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2013-08-22
Clifford Wolf
Added edif backend (still under construction)
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2013-08-21
Clifford Wolf
Merge pull request #10 from hansiglaser/master
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2013-08-21
Clifford Wolf
Some minor documentation fixes
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2013-08-21
Johann Glaser
fixed Verilog parser filename and line numbering issue...
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2013-08-20
Clifford Wolf
Merge pull request #9 from hansiglaser/master
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2013-08-20
Johann Glaser
Added support for include directories with the new...
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2013-08-20
Clifford Wolf
Merge pull request #8 from hansiglaser/master
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2013-08-20
Johann Glaser
Added support for notif0/notif1 primitives
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2013-08-20
Clifford Wolf
Added cleaning of old version_* files to version_*...
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2013-08-20
Clifford Wolf
Added version info to yosys command and added -V option
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2013-08-20
Clifford Wolf
Minor fixes in abc build instructions and abc pass
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2013-08-19
Clifford Wolf
Fixed width and sign detection for ** operator
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2013-08-19
Clifford Wolf
Added support for bufif0/bufif1 primitives
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2013-08-19
Clifford Wolf
Improved ast dumping (ast/verilog frontend)
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2013-08-15
Clifford Wolf
Implemented same div-by-zero behavior as found in other...
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2013-08-15
Clifford Wolf
Fixed signed div/mod in const eval (rounding and stuff)
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2013-08-15
Clifford Wolf
Added ezsat api for creation of anonymous vectors
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2013-08-15
Clifford Wolf
Added sat -ignore_div_by_zero switch
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