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microwatt.git
2022-08-09
Paul Mackerras
predecode: Add more comments to row_predecode_rom and...
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2022-08-09
Paul Mackerras
icache: Log 36 bits of instruction rather than 32
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2022-08-09
Paul Mackerras
predecode: Work around apparent yosys/nextpnr bug
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2022-08-09
Paul Mackerras
Pre-decode instructions when writing them to icache
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2022-08-09
Paul Mackerras
Eliminate use of primary opcode outside of decode1
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2022-08-09
Paul Mackerras
decode1: Divide insn_code values into ranges to indicat...
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2022-08-09
Paul Mackerras
decode1: Split instruction decoding into two steps
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2022-08-09
Paul Mackerras
decode1: Use block RAMs in decode
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2022-08-09
Paul Mackerras
decode2: Decode unit and single-pipe attributes for...
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2022-08-09
Paul Mackerras
FPU: Set sign of 0 result of subtraction in pack_dp
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2022-08-09
Paul Mackerras
FPU: Simplify IDLE state code
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2022-08-09
Paul Mackerras
FPU: Make an explicit exponent data path
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2022-08-09
Paul Mackerras
FPU: Minor fix and simplifications
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2022-08-09
Paul Mackerras
loadstore1: Simplify address generation in OP_FETCH_FAI...
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2022-08-09
Paul Mackerras
Remove leftover logic for 16-byte loads and stores
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2022-08-09
Paul Mackerras
writeback: Eliminate unintentional inferred latch
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2022-08-09
Michael Neuling
Merge pull request #390 from shenki/fix-whide-warnings
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2022-08-09
Anton Blanchard
Merge pull request #389 from paulusmack/fix-sc
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2022-08-09
Paul Mackerras
execute1: Fix trace interrupt on sc instruction
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2022-08-08
Joel Stanley
soc: Fix -Whide warning
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2022-08-08
Joel Stanley
xics: Fix -Whide warnings
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2022-08-08
Joel Stanley
fpu: Fix -Whide warnings
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2022-08-08
Michael Neuling
Merge pull request #387 from antonblanchard/gitignore
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2022-08-07
Anton Blanchard
Add litesdcard/build to gitignore
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2022-08-05
Paul Mackerras
Merge pull request #384 from antonblanchard/litedram...
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2022-08-04
Anton Blanchard
litedram: Regenerate
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2022-08-04
Anton Blanchard
litedram: MIGEN_GIT_SHA1 no longer defined
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2022-08-04
Paul Mackerras
Merge pull request #383 from antonblanchard/fix-sdcard
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2022-08-04
Anton Blanchard
litesdcard: Fix and regenerate Verilog
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2022-08-01
Paul Mackerras
Merge pull request #381 from shingarov/gitignore-artifacts
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2022-08-01
Paul Mackerras
Merge pull request #378 from mikey/ux-cleanup
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2022-07-29
Boris Shingarov
Gitignore build artifacts
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2022-07-28
Michael Neuling
test: Add test for metavalues
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2022-07-28
Michael Neuling
tests: Update FPU test output
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2022-07-28
Michael Neuling
tests: Minor script cleanups
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2022-07-28
Michael Neuling
Metavalue cleanup for register_file.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for pmu.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for rotator.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for mmu.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for loadstore1.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for icache.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for fpu.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for fetch1.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for execute1.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for decoder1.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for helpers.vhdl
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2022-07-28
Michael Neuling
Metavalue cleanup for common.vhdl
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2022-07-26
Michael Neuling
Merge pull request #379 from paulusmack/master
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2022-07-25
Michael Neuling
Merge pull request #380 from iagocaran/master
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2022-07-25
Michael Neuling
tests/pmu: Cleanup whitespace in pmc.c
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2022-07-22
Paul Mackerras
Use register addresses from decode1 for dependency...
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2022-07-22
Paul Mackerras
register_file: Make read access to register file synchr...
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2022-07-22
Paul Mackerras
decode1: Work out register addresses in decode1
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2022-07-22
Paul Mackerras
loadstore1: Do SPR reading in stage 2 rather than stage 3
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2022-07-22
Paul Mackerras
Provide debug access to SPRs in loadstore1 and mmu
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2022-07-22
Paul Mackerras
Restore debug access to SPRs
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2022-07-22
Paul Mackerras
Finish off taking SPRs out of register file
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2022-07-22
Paul Mackerras
Move LR, CTR and TAR out of the register file
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2022-07-22
Paul Mackerras
Start removing SPRs from register file
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2022-07-22
Paul Mackerras
Use FPU for division instructions if we have an FPU
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2022-07-22
Paul Mackerras
FPU: Add logic for 32-bit integer division
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2022-07-22
Paul Mackerras
FPU: Add integer division logic to FPU
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2022-07-22
Paul Mackerras
FPU: Convert internal R, A, B, and C registers to 8...
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2022-07-22
Paul Mackerras
Track hazards explicitly for XER overflow bits
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2022-07-22
Paul Mackerras
fetch1: Fix debug stop again
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2022-07-22
Paul Mackerras
control: Reimplement serialization using tags
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2022-07-22
Paul Mackerras
decode1: Remove stash buffer
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2022-07-22
Paul Mackerras
decode2: Rework to make the stall_out signal come from...
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2022-07-22
Paul Mackerras
Remove support for lq, stq, lqarx and stqcx.
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2022-07-22
Paul Mackerras
decode2: Rename 'r' to 'dc2'
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2022-07-22
Paul Mackerras
decode1: Reduce number of single-issue instructions
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2022-07-22
Paul Mackerras
FPU: Add stage-2 stall ability to FPU
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2022-07-22
Paul Mackerras
Do CR0 setting for Rc=1 instructions in execute2 instea...
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2022-07-22
Paul Mackerras
Allow integer instructions and load/store instructions...
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2022-07-22
Paul Mackerras
Add a bypass path from the execute2 stage
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2022-07-22
Paul Mackerras
Add a second execute stage to the pipeline
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2022-07-22
Paul Mackerras
execute1: Rename 'r' to 'ex1'
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2022-07-22
Paul Mackerras
execute1: Restructure to separate out execution of...
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2022-07-19
Iago Caran...
tests/pmu: Add load/store completed, instruction count...
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2022-06-29
Paul Mackerras
Move XER low bits out of register file
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2022-06-29
Paul Mackerras
Simplify flow control in the dcache and loadstore units
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2022-06-16
Paul Mackerras
Merge pull request #353 from tianrui-wei/master
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2022-06-16
Michael Neuling
Merge pull request #373 from antonblanchard/icache...
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2022-06-16
Michael Neuling
Merge pull request #376 from antonblanchard/loadstore...
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2022-06-16
Michael Neuling
Merge pull request #374 from antonblanchard/icache...
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2022-06-16
Michael Neuling
Merge pull request #364 from shenki/readme-updates
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2022-06-16
Michael Neuling
Merge pull request #372 from antonblanchard/dcache...
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2022-06-16
Michael Neuling
Merge pull request #371 from antonblanchard/unused-sig
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2022-06-16
Michael Neuling
Merge pull request #370 from antonblanchard/divider...
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2022-06-15
Paul Mackerras
Merge pull request #368 from antonblanchard/icache...
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2022-06-14
Anton Blanchard
Merge pull request #377 from antonblanchard/fpu-init
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2022-06-14
Anton Blanchard
fpu: Reduce uninitialised signals
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2022-06-14
Michael Neuling
Merge pull request #366 from antonblanchard/hello-world-bss
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2022-06-12
Anton Blanchard
Merge pull request #375 from antonblanchard/core_debug...
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2022-06-12
Anton Blanchard
loadstore1: reduce U state being output
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2022-06-12
Anton Blanchard
core_debug: Initialise gspr_index
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2022-06-12
Anton Blanchard
core: Remove unused icache_inv signal
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2022-06-12
Anton Blanchard
icache: Don't output X on i_out.insn
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2022-06-12
Anton Blanchard
dcache: remove unused do_write signal
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2022-06-12
Anton Blanchard
execute1: sub_mux_sel and result_mux_sel are unused
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