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yosys.git
2019-08-23
Eddie Hung
Forgot to slice
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2019-08-23
Eddie Hung
Cope with possibility that D could connect to Q on...
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2019-08-23
Eddie Hung
Mention shregmap -tech xilinx is superseded
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2019-08-23
Eddie Hung
xilinx_srl now copes with word-level flops $dff{,e}
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2019-08-23
Eddie Hung
xilinx_srl to use 'slice' features of pmgen for word...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgen...
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2019-08-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-23
Eddie Hung
Forgot one
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2019-08-23
Eddie Hung
Put abc_* attributes above port
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2019-08-23
Eddie Hung
Merge pull request #1326 from mmicko/doc-update
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2019-08-23
Clifford Wolf
Fix port hanlding in pmgen
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2019-08-23
Clifford Wolf
Add pmgen slices and choices
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2019-08-23
Miodrag Milanovic
Make macOS depenency clear
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2019-08-22
Eddie Hung
Do not propagate mem2reg attribute through to result
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2019-08-22
Eddie Hung
In sat: 'x' in init attr should not override constant
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2019-08-22
Eddie Hung
Remove Xilinx test
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2019-08-22
Eddie Hung
Actually, there might not be any harm in updating sigmap...
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2019-08-22
Eddie Hung
Add comment as per @cliffordwolf
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2019-08-22
Eddie Hung
Add shregmap -tech xilinx test
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2019-08-22
Eddie Hung
Revert "Try way that doesn't involve creating a new...
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2019-08-22
Eddie Hung
Try way that doesn't involve creating a new wire
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2019-08-22
Eddie Hung
If d_bit already in sigbit_chain_next, create extra...
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2019-08-22
Eddie Hung
Spelling
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2019-08-22
Eddie Hung
Merge pull request #1322 from mmicko/pyosys_osx
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2019-08-22
Eddie Hung
Add doc
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2019-08-22
Miodrag Milanovic
do not require boost if pyosys is not used
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2019-08-22
Eddie Hung
Merge pull request #1319 from TeaEngineering/shuckc...
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2019-08-22
Eddie Hung
Add copyright
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2019-08-22
Eddie Hung
Add CHANGELOG entry
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2019-08-22
Eddie Hung
Remove `shregmap -tech xilinx` additions
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2019-08-22
Eddie Hung
pmgen to also iterate over all module ports
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2019-08-22
Eddie Hung
Remove output_bits
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2019-08-22
Eddie Hung
Forgot to set ud_variable.minlen
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2019-08-22
Eddie Hung
Do not run xilinx_srl_pm in fixed loop
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-22
Eddie Hung
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
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2019-08-22
Clifford Wolf
Bump year in copyright notice
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2019-08-22
Clifford Wolf
Fix missing newline at end of file
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2019-08-22
Clifford Wolf
Merge pull request #1289 from mmicko/anlogic_fixes
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2019-08-22
Clifford Wolf
Fix missing newline at end of file
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2019-08-22
Clifford Wolf
Merge pull request #1281 from mmicko/efinix
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2019-08-22
Eddie Hung
Copy-paste typo
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2019-08-22
Chris Shucksmith
require tcl-tk in Brewfile
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2019-08-22
Eddie Hung
Respect opt_expr -keepdc as per @cliffordwolf
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2019-08-22
Eddie Hung
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
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2019-08-22
Eddie Hung
Add cover()
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2019-08-22
Eddie Hung
Canonical form
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2019-08-22
Clifford Wolf
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg
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2019-08-22
Eddie Hung
Add test
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2019-08-22
Eddie Hung
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-22
Eddie Hung
Reuse var
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2019-08-22
Eddie Hung
Revert "Trim shiftx_width when upper bits are 1'bx"
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2019-08-22
Eddie Hung
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-22
Eddie Hung
Trim shiftx_width when upper bits are 1'bx
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2019-08-22
Eddie Hung
Add comment
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2019-08-22
Eddie Hung
Add variable length support to xilinx_srl
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2019-08-21
Eddie Hung
Rename pattern to fixed
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2019-08-21
Eddie Hung
attribute -> attr
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2019-08-21
Eddie Hung
Use Cell::has_keep_attribute()
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2019-08-21
Eddie Hung
abc9 to perform new 'map_ffs' before 'map_luts'
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2019-08-21
Eddie Hung
xilinx_srl to support FDRE and FDRE_1
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2019-08-21
Eddie Hung
Fix polarity of EN_POL
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2019-08-21
whitequark
Merge pull request #1315 from mmicko/fix_dependencies
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2019-08-21
Eddie Hung
Add CLKPOL == 0
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2019-08-21
Eddie Hung
Reject if not minlen from inside pattern matcher
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2019-08-21
Eddie Hung
Get wire via SigBit
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2019-08-21
Eddie Hung
Respect \keep on cells or wires
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2019-08-21
Eddie Hung
Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
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2019-08-21
Eddie Hung
mem2reg to preserve user attributes and src
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2019-08-21
Eddie Hung
Add init support
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2019-08-21
Eddie Hung
Fix spacing
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2019-08-21
Eddie Hung
Initial progress on xilinx_srl
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2019-08-21
Miodrag Milanovic
Fix test_pmgen deps
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2019-08-21
Clifford Wolf
Merge pull request #1314 from YosysHQ/eddie/fix_techmap
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2019-08-21
Eddie Hung
Missing newline
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2019-08-21
Eddie Hung
Fix copy-paste typo
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2019-08-21
Eddie Hung
Grammar
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2019-08-21
Eddie Hung
Add test
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2019-08-21
Eddie Hung
techmap -max_iter to apply to each module individually
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2019-08-20
Eddie Hung
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
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2019-08-20
Eddie Hung
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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2019-08-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-20
Clifford Wolf
Merge pull request #1298 from YosysHQ/clifford/pmgen
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2019-08-20
Clifford Wolf
Merge branch 'master' into clifford/pmgen
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2019-08-20
Clifford Wolf
Add test case for real parameters
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2019-08-20
Clifford Wolf
Merge pull request #1308 from jakobwenzel/real_params
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2019-08-20
whitequark
Merge pull request #1309 from whitequark/proc_clean...
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2019-08-19
Eddie Hung
Fix typo
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2019-08-19
Eddie Hung
Fix typo
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2019-08-19
Eddie Hung
ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
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2019-08-19
Eddie Hung
Clarify with 'only'
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2019-08-19
Eddie Hung
Update doc
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2019-08-19
Eddie Hung
Unify abc_carry_{in,out} into abc_carry and use port...
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2019-08-19
whitequark
proc_clean: fix order of switch insertion.
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2019-08-19
Jakob Wenzel
handle real values when deriving ast modules
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2019-08-19
Clifford Wolf
Merge pull request #1306 from mmicko/gitignore_fix
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2019-08-19
Clifford Wolf
Add *.sv to tests/simple_abc9/.gitignore
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2019-08-19
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-08-19
Clifford Wolf
Merge pull request #1305 from YosysHQ/clifford/testfast
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