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yosys.git
2019-08-09
Eddie Hung
Add more comments
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2019-08-08
Eddie Hung
Add a few comments to document $alu and $lcu
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2019-08-07
Eddie Hung
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup
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2019-08-07
Eddie Hung
Add comment
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2019-08-07
Eddie Hung
Revert "Add TODO"
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2019-08-07
Eddie Hung
Add TODO
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2019-08-07
Eddie Hung
Compute box_lookup just once
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2019-08-07
Eddie Hung
Run "clean" on mapped_mod in its own design
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2019-08-07
Eddie Hung
Run "clean -purge" on holes_module in its own design
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2019-08-07
David Shah
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
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2019-08-07
David Shah
ecp5: Make cells_sim.v consistent with nextpnr
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2019-08-07
Clifford Wolf
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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2019-08-07
Clifford Wolf
Merge pull request #1240 from ucb-bar/firrtl-properties...
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2019-08-07
Clifford Wolf
Merge pull request #1249 from mmicko/anlogic_fix
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2019-08-07
Clifford Wolf
Merge pull request #1252 from YosysHQ/clifford/fix1231
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2019-08-07
Clifford Wolf
Merge pull request #1253 from YosysHQ/clifford/check
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2019-08-07
Clifford Wolf
Merge pull request #1257 from YosysHQ/clifford/cellcosts
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2019-08-07
David Shah
Update CHANGELOG
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2019-08-07
David Shah
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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2019-08-07
Clifford Wolf
Tweak default gate costs, cleanup "stat -tech cmos"
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2019-08-06
Clifford Wolf
Redesign of cell cost API
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2019-08-06
Eddie Hung
Add signed opt_expr tests
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2019-08-06
Eddie Hung
Add signed test
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2019-08-06
Eddie Hung
Move LSB-trimming functionality from wreduce to opt_expr
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2019-08-06
Eddie Hung
Add SigSpec::extract_end() convenience function
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2019-08-06
Eddie Hung
Restore original SigSpec::extract()
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2019-08-06
Eddie Hung
Move LSB tests from wreduce to opt_expr
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2019-08-06
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-06
David Shah
Merge pull request #1232 from YosysHQ/dave/write_gzip
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2019-08-06
Clifford Wolf
Be less aggressive with running design->check()
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2019-08-06
David Shah
Add test for writing gzip-compressed files
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2019-08-06
David Shah
Add support for writing gzip-compressed files
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2019-08-06
Clifford Wolf
Fix handling of functions/tasks without top-level begin...
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2019-08-06
Clifford Wolf
Merge pull request #1251 from YosysHQ/clifford/nmux
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2019-08-06
Clifford Wolf
Add $_NMUX_, add "abc -g cmos", add proper cmos cell...
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2019-08-03
Miodrag Milanovic
anlogic : Fix alu mapping
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2019-08-03
whitequark
Merge pull request #1242 from jfng/fix-proc_prune-partial
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2019-08-02
Clifford Wolf
Merge pull request #1238 from mmicko/vsbuild_fix
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2019-08-02
Clifford Wolf
Merge pull request #1239 from mmicko/mingw_fix
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2019-08-01
Eddie Hung
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
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2019-08-01
Miodrag Milanovic
Fix linking issue for new mxe and pthread
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2019-08-01
Miodrag Milanovic
Fix yosys linking for mxe
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2019-08-01
Miodrag Milanovic
New mxe hacks needed to support 2ca237e
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2019-08-01
Miodrag Milanovic
Fix formatting for msys2 mingw build using GetSize
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2019-08-01
Jean-François...
proc_prune: Promote partially redundant assignments.
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2019-08-01
Clifford Wolf
Update JSON front-end to process new attr/param encoding
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2019-08-01
Clifford Wolf
Implement improved JSON attr/param encoding
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2019-07-31
Jim Lawson
Support explicit FIRRTL properties for better accommoda...
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2019-07-31
Clifford Wolf
Merge pull request #1233 from YosysHQ/clifford/defer
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2019-07-31
Miodrag Milanovic
Visual Studio build fix
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2019-07-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-07-29
Eddie Hung
RST -> RSTBRST for RAMB8BWER
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2019-07-29
Eddie Hung
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
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2019-07-29
David Shah
Merge pull request #1234 from mmicko/fix_gzip_no_exist
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2019-07-29
Miodrag Milanovic
Fix case when file does not exist
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2019-07-29
Clifford Wolf
Update README to use "read" instead of "read_verilog"
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2019-07-29
Clifford Wolf
Call "read_verilog" with -defer from "read"
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2019-07-27
David Shah
Merge pull request #1226 from YosysHQ/dave/gzip
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2019-07-26
David Shah
Update CHANGELOG
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2019-07-26
David Shah
verilog_lexer: Increase YY_BUF_SIZE to 65536
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2019-07-26
David Shah
Fix frontend auto-detection for gzipped input
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2019-07-26
David Shah
Add support for reading gzip'd input files
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2019-07-25
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-07-25
Eddie Hung
Bump abc to fix &mfs bug
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2019-07-25
Clifford Wolf
Merge branch 'ZirconiumX-synth_intel_m9k'
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2019-07-25
Clifford Wolf
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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2019-07-25
Clifford Wolf
Merge pull request #1219 from jakobwenzel/objIterator
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2019-07-25
Eddie Hung
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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2019-07-25
Jakob Wenzel
replaced std::iterator with using statements
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2019-07-25
David Shah
xilinx: Fix missing cell name underscore in cells_map.v
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2019-07-24
Eddie Hung
Merge pull request #1222 from koriakin/s6-example
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2019-07-24
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-07-24
Marcin Kościelnicki
Add a simple example for Spartan 6
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2019-07-24
Jakob Wenzel
made ObjectIterator extend std::iterator
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2019-07-24
Dan Ravensloft
intel: Make -noiopads the default
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2019-07-23
Dan Ravensloft
intel: Map M9K BRAM only on families that have it
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2019-07-23
Eddie Hung
Merge pull request #1212 from YosysHQ/eddie/signed_ice4...
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2019-07-22
Eddie Hung
Merge pull request #1214 from jakobwenzel/astmod_clone
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2019-07-22
Jakob Wenzel
initialize noblackbox and nowb in AstModule::clone
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2019-07-20
Clifford Wolf
Add "stat -tech cmos"
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2019-07-19
Eddie Hung
Try and fix again
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2019-07-19
Eddie Hung
Add another test
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2019-07-19
Eddie Hung
Do not access beyond bounds
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2019-07-19
Eddie Hung
Add an SigSpec::at(offset, defval) convenience method
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2019-07-19
Eddie Hung
Wrap A and B in sigmap
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2019-07-19
Eddie Hung
Remove "top" from message
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2019-07-19
Eddie Hung
Also optimise MSB of $sub
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2019-07-19
Eddie Hung
Add one more test with trimming Y_WIDTH of $sub
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2019-07-19
Eddie Hung
Be more explicit
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2019-07-19
Eddie Hung
wreduce for $sub
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2019-07-19
Eddie Hung
Add tests for sub too
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2019-07-19
Eddie Hung
Add test
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2019-07-19
Eddie Hung
SigSpec::extract to take negative lengths
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2019-07-19
David Shah
ice40: Fix test_dsp_model.sh
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2019-07-19
David Shah
ice40/cells_sim.v: Fix sign of J and K partial products
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2019-07-19
David Shah
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
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2019-07-19
Eddie Hung
Add tests for all combinations of A and B signedness...
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2019-07-19
Eddie Hung
Don't copy ref if exists already
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2019-07-18
David Shah
Merge pull request #1208 from ZirconiumX/intel_cleanups
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2019-07-18
Dan Ravensloft
synth_intel: Use stringf
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